參數(shù)資料
型號: XWM8711EDS
廠商: Wolfson Microelectronics
英文描述: Internet Audio DAC with Integrated Headphone Driver
中文描述: 互聯(lián)網(wǎng)音頻DAC集成耳機(jī)驅(qū)動器
文件頁數(shù): 30/36頁
文件大?。?/td> 379K
代理商: XWM8711EDS
WM8711
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
30
REGISTER
ADDRESS
0000111
Digital Audio
Interface Format
BIT
LABEL
DEFAULT
DESCRIPTION
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
DACLRC phase control (in left, right
or I
S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I
2
S mode)
or
DSP mode A/B select ( in DSP mode
only)
1 = MSB is available on 2
nd
BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
3:2
IWL[1:0]
10
4
LRP
0
5
LRSWAP
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
1 = Invert BCLK
0 = Don
t invert BCLK
Mode Select
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
USB Mode
0 = 250fs
1 = 272fs
DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Core Clock divider select
1 = Core Clock is MCLK divide by 2
0 = Core Clock is MCLK
CLKOUT divider select
1 = CLOCKOUT is MCLK divide by 2
0 = CLOCKOUT is MCLK
6
MS
0
7
BCLKINV
0
0
USB/
NORMAL
0
1
BOSR
0
Normal Mode
0 = 256fs
1 = 384fs
5:2
SR[3:0]
0000
6
CLKIDIV2
0
0001000
Sampling
Control
7
CLKODIV2
0
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