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參數(shù)資料
| 型號： | Z53C80SCSI |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| 中文描述： | 小型計算機(jī)系統(tǒng)接口（SCSI） |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 447K |
| 代理商： | Z53C80SCSI |
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11
Z53C80 SCSI
Z
ILOG
PS97SCC0200
Bit 7.
Last Byte Sent(Read Only). The End Of DMA
Transfer bit (Bus and Status Register, bit 7) only indicates
when the last byte was received from the DMA controller.
The Last Byte Sent bit can be used to flag that the last byte
of the DMA send operation has been transferred on the
SCSI Data Bus.
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
Address: 4
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Address: 4
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"X"
Last Byte Sent
Address: 3
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 11. Target Command Register
Current SCSI Bus Status Register.
Address 4(Read
Only). The Current SCSI Bus Register is a read-only
register which is used to monitor seven SCSI Bus control
signals, plus the Data Bus parity bit. For example, an
Initiator device can use this register to determine the
current bus phase and to poll /REQ for pending data
transfers. This register may also be used to determine why
a particular interrupt occurred. Figure 12 describes the
Current SCSI Bus Status Register.
Select Enable Register.
Address 4(Write Only). The
Select Enable Register (Figure 13) is a write-only register
which is used as a mask to monitor a signal ID during a
selection attempt. The simultaneous occurrence of the
correct ID bit, /BSY FALSE, and /SEL TRUE will cause an
interrupt. This interrupt can be disabled by resetting all bits
in this register. If the Enable Parity Checking bit (Mode
Register, bit 5) is active (1), parity is checked during
selection.
Figure 12. Current SCSI Bus Status Register
Figure 13. Select Enable Register
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