參數(shù)資料
型號(hào)： Z53C80SCSI
廠商： ZiLOG, Inc.
英文描述： SMALL COMPUTER SYSTEM INTERFACE (SCSI)
中文描述： 小型計(jì)算機(jī)系統(tǒng)接口（SCSI）
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 447K
代理商： Z53C80SCSI
15
Z53C80 SCSI
Z
ILOG
PS97SCC0200
D7
D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
X
1
1
1
0
X
X
Figure 19. Bus and Status Register
Figure 20. Current SCSI Bus Status Register
Parity Error.
An interrupt is generated for a received parity
error it the Enable Parity Check (bit 5) and the Enable Parity
Interrupt (bit 4) bits are set (1) in the Mode Register. Parity
is checked during a read of the Current SCSI Data Register
and during a DMA receive operation. A parity error can be
detected without generating an interrupt by disabling the
Enable Parity Interrupt bit and checking the Parity Error
flag (Bus and Status Register, bit 5).
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
21 and 22, respectively.
Figure 21. Bus and Status Register
Figure 22. Current SCSI Bus Status Register
Bus Phase Mismatch.
The SCSI phase lines have the
signals I//O, C//D, and /MSG. These signals are compared
with the corresponding bits in the Target Command
Register: Assert I//O (bit 0), Assert C//D (bit 1), and Assert
/MSG (bit 2). The comparison occurs continually and is
reflected in the Phase Match bit (bit 3) of the Bus and Status
Register. If the DMA Mode bit (Mode Register, bit 1) is
active and a phase mismatch occurs when /REQ transitions
from False to True, an interrupt (IRQ) is generated.
D7
D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
X
0
1
X
0
X
X
D7
D0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
X
X
X
X
X
X
X
X
D7
D0
/DBP
/SEL
I//O
C//D
/MSQ
/REQ
/BSY
/RST
0
1
1
X
X
X
0
X
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