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| 型號(hào)： | Z8S18006PEC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 15/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006PEC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-15
1
M1TE (M1 Temporary Enable).
This bit controls the tem-
porary assertion of the /M1 signal. It is always read back
as a 1 and is set to 1 during reset.
When M1E is set to 0 to accommodate certain external
Z80 peripheral(s), those same device(s) may require a
pulse on M1 after programming certain of their registers to
complete the function being programmed.
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until
the PIO sees an active M1 signal. When M1TE=1, there is
no change in the operation of the /M1 signal and M1E con-
trols its function. When M1TE=0, the M1 output will be as-
serted during the next opcode fetch cycle regardless of the
state programmed into the M1E bit. This is only momen-
tary (one time) and the user need not preprogram a 1 to
disable the function (see Figure10).
Figure 9. RETI Instruction Sequence with MIE=0
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
T
I
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
A
0
-A
18
(A
19
)
φ
D
0
-D
7
PC
PC+1
PC
PC+1
EDH
4DH
EDH
4DH
MREQ
M1
RD
ST
Table 4. RETI Control Signal States with MIE=0
Machine
Cycle
1
2
M1
States
T1-T3
T1-T3
Ti
Ti
Ti
T1-T3
Ti
T1-T3
T1-T3
T1-T3
Address
1st Opcode
2nd Opcode
NA
NA
NA
1st Opcode
NA
2nd Opcode
SP
SP+1
Data
EDH
4DH
Tri-State
Tri-State
Tri-State
EDH
Tri-State
4DH
Data
Data
RD
0
0
1
1
1
0
1
0
0
0
WR
1
1
1
1
1
1
1
1
1
1
MREQ
0
0
1
1
1
0
1
0
0
0
IORQ
1
1
1
1
1
1
1
1
1
1
IOC=1
0
0
1
1
1
0
1
0
1
1
IOC=0
1
1
1
1
1
0
1
1
1
1
HALT
1
1
1
1
1
1
1
1
1
1
ST
0
0
1
1
1
1
1
1
1
1
3
4
5
6
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