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| 型號： | Z8S18006PEC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| 中文描述： | 強化Z180微處理器 |
| 文件頁數(shù)： | 17/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006PEC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-17
1
HALT and Low-Power Operating Modes.
The
Z80180/Z8S180/Z8L180 can operate in seven modes with
respect to activity and power consumption:
–
–
–
–
–
–
–
Normal Operation
HALT Mode
IOSTOP Mode
SLEEP Mode
SYSTEM STOP Mode
IDLE Mode
STANDBY Mode (with or without QUICK
RECOVERY)
Normal Operation.
The Z80180/Z8S180/Z8L180 proces-
sor is fetching and running a program. All enabled func-
tions and portions of the device are active, and the HALT
pin is High.
HALT Mode.
This mode is entered by the HALT instruc-
tion. Thereafter, the Z80180/Z8S180/Z8L180 processor
continually fetches the following opcode but does not exe-
cute it, and drives the HALT, ST and M1 pins all Low. The
oscillator and PHI pin remain active, interrupts and bus
granting to external masters, and DRAM refresh can occur
and all on-chip I/O devices continue to operate including
the DMA channels.
The Z80180/Z8S180/Z8L180 leaves HALT mode in re-
sponse to a Low on RESET, on to an interrupt from an en-
abled on-chip source, an external request on NMI, or an
enabled external request on INT0, INT1, or INT2. In case
of an interrupt, the return address will be the instruction fol-
lowing the HALT instruction; at that point the program can
either branch back to the HALT instruction to wait for an-
other interrupt, or can examine the new state of the sys-
tem/application and respond appropriately.
SLEEP Mode.
This mode is entered by keeping the
IOSTOP bit (ICR5) bits 3 and 6 of the CPU Control Regis-
ter (CCR3, CCR6) all zero and executing the SLP instruc-
tion. The oscillator and PHI output continue operating, but
are blocked from the CPU core and DMA channels to re-
duce power consumption. DRAM refresh stops but inter-
rupts and granting to external master can occur. Except
when the bus is granted to an external master, A19-0 and
all control signals except /HALT are maintained High.
/HALT is Low. I/O operations continue as before the SLP
instruction, except for the DMA channels.
The Z80180/Z8S180/Z8L180 leaves SLEEP mode in re-
sponse to a low on /RESET, an interrupt request from an
on-chip source, an external request on /NMI, or an external
request on /INT0, 1, or 2.
Figure 13. HALT Timing
INT
i
, NMI
A
0
-A
19
/HALT
/M1
/MREQ
/RD
HALT Opcode Address
HALT Opcode Address + 1
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相關代理商/技術參數(shù) |
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| Z8S18006PSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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