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| 型號： | Z8S18006PEC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| 中文描述： | 強化Z180微處理器 |
| 文件頁數(shù)： | 58/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006PEC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-58
P R E L I M I N A R Y
DS971800401
DMA/WAIT CONTROL REGISTER (DCNTL)
DCNTL controls the insertion of wait states into DMAC
(and CPU) accesses of memory or I/O. Also, it defines the
Request signal for each channel as level or edge sense.
DCNTL also sets the DMA transfer mode for channel 1,
which is limited to memory to/from I/O transfers.
MWI1, MWI0: Memory Wait Insertion (bits 7-6).
Speci-
fies the number of wait states introduced into CPU or
DMAC memory access cycles. MWI1 and MWI0 are set to
1 during RESET.
I
WI1, IWI0: I/O Wait Insertion (bits 5-4).
Specifies the
number of wait states introduced into CPU or DMAC I/O
access cycles. IWI1 and IWI0 are set to 1 during RESET.
See the section on Wait-State Generation for details.
DMS1, DMS0: DMA Request Sense (bits 3-2).
DMS1
and DMS0 specify the DMA request sense for channel 0
and channel 1 respectively. When reset to 0, the input is
level sense. When set to 1, the input is edge sense. DMS1
and DMS0 are cleared to 0 during RESET.
Typically, for an input/source device, the associated DMS
bit should be programmed as 0 for level sense because
the device has a relatively long time to update its Request
signal after the DMA channel reads data from it in the first
of the two machine cycles involved in transferring a byte.
An output/destination device has much less time to update
its Request signal, after the DMA channel starts a write op-
eration to it, as the second machine cycle of the two cycles
involved in transferring a byte. With zero-wait state I/O cy-
cles, which apply only to the ASCIs, it is impossible for a
device to update its Request signal in time, and edge sens-
ing must be used.
Figure 74. DMA/WAIT Control Register (DCNTL: I/O Address = 32H)
Bit
MWI1
IWI0
7
6
5
4
3
2
1
0
R/W
R/W
DMS1 DMS0
DIM1
R/W
R/W
R/W
MWI0
IWI1
DIM0
R/W
R/W
R/W
MWI1
0
0
1
1
MWI0
0
1
0
1
Wait State
0
1
2
3
IWI1
0
0
1
1
IWI0
0
1
0
1
Wait State
0
2
3
4
DMSi
1
0
Sense
Edge Sense
Level Sense
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相關(guān)代理商/技術(shù)參數(shù) |
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| Z8S18006PSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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| Z8S18008FEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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