- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373771 > Z8S18006PEC (ZiLOG, Inc.) CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 PDF資料下載
參數(shù)資料
| 型號(hào)： | Z8S18006PEC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁(yè)數(shù)： | 44/70頁(yè) |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006PEC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-44
P R E L I M I N A R Y
DS971800401
Transmit Enable (bit 4).
A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears TE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. TE and RE
are never both set to 1 at the same time. TE is cleared to
0 during RESET and IOSTOP mode.
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0).
SS2, SS1 and
SS0 select the CSI/O transmit/receive clock source and
speed. SS2, SS1 and SS0 are all set to 1 during RESET.
Table 10 shows CSI/O Baud Rate Selection.
After RESET, the CKS pin is configured as an external
clock input (SS2, SS1, SS0 = 1). Changing these values
causes CKS to become an output pin and the selected
clock is output when transmit or receive operations are en-
abled.
CSI/O Transmit/Receive Data Register
(TRDR: I/O Address = 0BH).
Timer Data Register Channel 0L
TMDR0L
0CH
Timer Data Register Channel 0H
TMDR0H
0D H
Table 7. CSI/O Baud Rate Selection
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Divide Ratio
÷
20
÷
40
÷
80
÷
160
÷
320
÷
640
÷
1280
External Clock Input
(less than
÷
20.)
Figure 41. CSI/O Transmit/Receive Data Register 1R
CSI/O T/R Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 42. Timer Register Channel OL
Figure 43. Timer Data Register Channel OH
ASCI Receive Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Timer Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z8S18006PSC | CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE |
| Z90102 | CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90103 | CAP 680PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90104 | CAP 820PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90110 | CAP 1000PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S18006PSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006VEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006VSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008FEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。