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參數(shù)資料
| 型號(hào)： | Z8S18033PSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ENHANCED Z180 MICROPROCESSOR |
| 中文描述： | 8-BIT, MICROPROCESSOR, PDIP64 |
| 封裝： | PLASTIC, DIP-64 |
| 文件頁數(shù)： | 38/70頁 |
| 文件大小： | 387K |
| 代理商： | Z8S18033PSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-38
P R E L I M I N A R Y
DS971800401
The following paragraphs explain the various functions of
the ASCI registers.
ASCI Transmit Register 0.
When the ASCI Transmit
Register receives data from the ASCI Transmit Data Reg-
ister (TDR), the data is shifted out to the TxA pin. When
transmission is completed, the next byte (if available) is
automatically loaded from TDR into TSR and the next
transmission starts. If no data is available for transmission,
TSR IDLEs by outputting a continuous High level. This reg-
ister is not program accessible
ASCI Transmit Data Register 0,1 (TDR0, 1: I/O address
= 06H, 07H).
Data written to the ASCI Transmit Data Reg-
ister is transferred to the TSR as soon as TSR is empty.
Data can be written while TSR is shifting out the previous
byte of data. Thus, the ASCI transmitter is double buffered.
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation will not be af-
fected by this read operation
ASCI Receive Shift Register 0,1 (RSR0,1).
This register
receives data shifted in on the RxA pin. When full, data is
automatically transferred to the ASCI Receive Data Regis-
ter (RDR) if it is empty. If RSR is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
ASCI Receive Data FIFO 0,1 (RDR0, 1:I/O Address = 08H,
09H). The ASCI Receive Data Register is a read-only reg-
ister. When a complete incoming data byte is assembled
in RSR, it is automatically transferred to the 4 character
Receive Data First-In First-Out (FIFO) memory. The oldest
character in the FIFO (if any) can be read from the Receive
Data Register (RDR). The next incoming data byte can be
shifted into RSR while the FIFO is full. Thus, the ASCI re-
ceiver is well buffered.
ASCI STATUS FIFO
This 4 entry FIFO contains Parity Error, Framing Error, Rx
Overrun, and Break status bits associated with each char-
acter in the receive data FIFO. The status of the oldest
character (if any) can be read from the ASCI status regis-
ters as described below
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z8S18033VEC | CONN HDR INVERSE 30POS 5ROW R/A |
| Z8S18033VSC | CONN HDR INVERSE 120POS 5ROW R/A |
| Z8S180 | CAP 0.1UF 100V +80-20% Z5U AXIAL TR-14 |
| Z8S18006FEC | CAP 1UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006FSC | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S18033VEC | 功能描述:微處理器 - MPU 33MHz STATIC Z180 XT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| Z8S18033VEC00TR | 功能描述:IC Z180 MPU 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| Z8S18033VEG | 功能描述:微處理器 - MPU 33MHz STATIC Z180 XT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| Z8S18033VSC | 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| Z8S180-33VSC | 制造商:Zilog Inc 功能描述:IC CPU (Z80B) SMD 8S180 PLCC68 |
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