參數(shù)資料
型號(hào): Z8S18033PSC
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: ENHANCED Z180 MICROPROCESSOR
中文描述: 8-BIT, MICROPROCESSOR, PDIP64
封裝: PLASTIC, DIP-64
文件頁數(shù): 61/70頁
文件大?。?/td> 387K
代理商: Z8S18033PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-61
1
REFRESH CONTROL REGISTER
Mnemonic RCR
Address 36
The RCR specifies the interval and length of refresh cy-
cles, while enabling or disabling the refresh function.
REFE: Refresh Enable (bit 7).
REFE = disables the re-
fresh controller while REFE = 1 enables refresh cycle in-
sertion. REFE is set to 1 during RESET.
REFW: Refresh Wait (bit 6).
REFW = 0 causes the re-
fresh cycle to be two clocks in duration. REFW = 1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (TRW). REFW is set to 1 during RESET.
CYC1, 0: Cycle Interval (bit 1,0).
CYC1 and CYC0 spec-
ify the interval (in clock cycles) between refresh cycles. In
the case of dynamic RAMs requiring 128 refresh cycles ev-
ery 2 ms (0r 256 cycles in every 4 ms), the required refresh
interval is less than or equal to 15.625
μ
s. Thus, the under-
lined values indicate the best refresh interval depending
on CPU clock frequency. CYC0 and CYC1 are cleared to
0 during RESET (see Table 14).
Figure 77. TRAP Timing-3
rd
Opcode Undefined
T
1
T
2
T
3
T
1
T
2
T
TP
T
3
T
i
T
i
T
1
T
2
T
3
T
2
T
3
T
1
T
1
T
2
A
0
-A
18
(A
19
)
φ
D
0
-D
7
PC
0000H
SP-1
Undefined
Opcode
MREQ
M1
RD
WR
T
3
SP-2
PC-1
H
PC-1
L
3nd Opcode
Fetch Cycle
PC Stacking
Opcode
Fetch Cycle
Restart
from 0000H
Memory
Read Cycle
IX + d, IY + d
T
i
T
i
Figure 78. Refresh Control Register
(RCA: I/O Address = 36H)
Reserved
--
--
--
--
--
--
--
7
-
6
5
4
3
2
1
Cyc1
Cyc0
REFW
REFE
--
0
相關(guān)PDF資料
PDF描述
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