參數(shù)資料
型號(hào)： Z8S18033PSC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： ENHANCED Z180 MICROPROCESSOR
中文描述： 8-BIT, MICROPROCESSOR, PDIP64
封裝： PLASTIC, DIP-64
文件頁(yè)數(shù)： 59/70頁(yè)
文件大?。?/td> 387K
代理商： Z8S18033PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-59
1
With one-wait-state I/O cycles (the fastest possible except
for the ASCIs), it is unlikely that an output device will be
able to update its Request in time, and edge sense is re-
quired.
DIM1, DIM0: DMA Channel 1 I/O and Memory Mode
(bits 1-0).
Specifies the source/destination and address
modifier for channel 1 memory to/from I/O transfer modes.
DIM1 and DIM0 are cleared to 0 during RESET.
INTERRUPT VECTOR LOW REGISTER
Mnemonic: IL
Address 33
Bits 7-5 of IL are used as bits 7-5 of the synthesized inter-
rupt vector during interrupts for the INT1 and INT2 pins
and for the DMAs, ASCIs, PRTs, and CSI/O. These three
bits are cleared to 0 during Reset (Figure 75).
INT/TRAP CONTROL REGISTER
Mnemonics ITC
Address 34
INT/TRAP Control Register (ITC, I/O Address 34H).
This register is used in handling TRAP interrupts and to
enable or disable Maskable Interrupt Level 0 and the INT1
and INT2 pins.
TRAP (bit 7).
This bit is set to 1 when an undefined Op-
code is fetched. TRAP can be reset under program control
by writing it with a 0, however, it cannot be written with 1
under program control. TRAP is reset to 0 during RESET.
UFO: Undefined Fetch Object (bit 6).
When a TRAP in-
terrupt occurs, the contents of UFO allow determination of
the starting address of the undefined instruction. This is
necessary since the TRAP may occur on either the second
or third byte of the Opcode. UFO allows the stacked PC
value to be correctly adjusted. If UFO = 0, the first Opcode
should be interpreted as the stacked PC-1. If UFO = 1, the
first Opcode address is stacked PC-2. UFO is Read-Only.
ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0).
ITE2 and
ITE1 enable and disable the external interrupt inputs /INT2
and /INT1, respectively. ITE0 enables and disables inter-
rupts from the on-chip ESCC, CTCs and Bidirectional Cen-
tronics controller as well as the external interrupt input
/INT0. A 1 in a bit enables the corresponding interrupt level
while a 0 disables it. A Reset sets ITE0 to 1 and clears
ITE1 and ITE2 to 0.
TRAP Interrupt.
The Z80180/Z8S180/Z8L180 generates
a non-maskable (not affected by the state of IEF1) TRAP
interrupt when an undefined Opcode fetch occurs. This
feature can be used to increase software reliability, imple-
ment an “extended” instruction set, or both. TRAP may oc-
cur during Opcode fetch cycles and also if an undefined
Table 13. Channel 1 Transfer Mode
Address
DIM1 DMI0 Transfer Mode
0
0
0
1
1
0
1
1
Increment/Decrement
MAR1 +1, IAR1 fixed
MAR1–1, IAR1 fixed
IAR1 fixed, MAR1 + 1
IAR1 fixed, MAR1 –1
Memory
→
I/O
Memory
→
I/O
I/O
→
Memory
I/O
→
Memory
Figure 75. Interrupt Vector Low Register (IL: I/O Address = 33H)
Bit
IL 7
IL 6
Interrupt Source Dependent Code
IL 5
7
6
5
4
3
2
1
0
––
––
R/W
R/W
––
––
––
R/W
Programmable
Bit
TRAP UFO
R/W R/W R/W
––
7
6
5
4
3
2
1
0
––
––
ITE2 ITE1 ITE0
R/W
R
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Z8S18033VEC00TR 功能描述:IC Z180 MPU 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
Z8S18033VEG 功能描述:微處理器 - MPU 33MHz STATIC Z180 XT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S18033VSC 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S180-33VSC 制造商:Zilog Inc 功能描述:IC CPU (Z80B) SMD 8S180 PLCC68
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