參數(shù)資料
型號(hào): Z8S18033VSC
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: CONN HDR INVERSE 120POS 5ROW R/A
中文描述: 8-BIT, MICROPROCESSOR, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 44/70頁
文件大?。?/td> 387K
代理商: Z8S18033VSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-44
P R E L I M I N A R Y
DS971800401
Transmit Enable (bit 4).
A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears TE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. TE and RE
are never both set to 1 at the same time. TE is cleared to
0 during RESET and IOSTOP mode.
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0).
SS2, SS1 and
SS0 select the CSI/O transmit/receive clock source and
speed. SS2, SS1 and SS0 are all set to 1 during RESET.
Table 10 shows CSI/O Baud Rate Selection.
After RESET, the CKS pin is configured as an external
clock input (SS2, SS1, SS0 = 1). Changing these values
causes CKS to become an output pin and the selected
clock is output when transmit or receive operations are en-
abled.
CSI/O Transmit/Receive Data Register
(TRDR: I/O Address = 0BH).
Timer Data Register Channel 0L
TMDR0L
0CH
Timer Data Register Channel 0H
TMDR0H
0D H
Table 7. CSI/O Baud Rate Selection
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Divide Ratio
÷
20
÷
40
÷
80
÷
160
÷
320
÷
640
÷
1280
External Clock Input
(less than
÷
20.)
Figure 41. CSI/O Transmit/Receive Data Register 1R
CSI/O T/R Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 42. Timer Register Channel OL
Figure 43. Timer Data Register Channel OH
ASCI Receive Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Timer Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
相關(guān)PDF資料
PDF描述
Z8S180 CAP 0.1UF 100V +80-20% Z5U AXIAL TR-14
Z8S18006FEC CAP 1UF 50V 10% X7R AXIAL TR-14
Z8S18006FSC CAP 0.47UF 50V 10% X7R AXIAL TR-14
Z8S18006PEC CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14
Z8S18006PSC CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Z8S180-33VSC 制造商:Zilog Inc 功能描述:IC CPU (Z80B) SMD 8S180 PLCC68
Z8S18033VSC00TR 功能描述:IC Z180 MPU 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE(27x27) 包裝:托盤
Z8S18033VSG 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S18033VSG00TR 制造商:Zilog Inc 功能描述:Z8S180 Series 33 MHz 5 V Enhanced Microprocessor - PLCC - 68
Z8S2128C 制造商:STEC Inc 功能描述:128GB,ZEUS SATA SSD,14.5MM - Bulk