參數(shù)資料
型號： Z8S18033VSC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： CONN HDR INVERSE 120POS 5ROW R/A
中文描述： 8-BIT, MICROPROCESSOR, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 62/70頁
文件大小： 387K
代理商： Z8S18033VSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-62
P R E L I M I N A R Y
DS971800401
Refresh Control and Reset.
After RESET, based on the
initialized value of RCR, refresh cycles will occur with an
interval of 10 clock cycles and be 3 clock cycles in dura-
tion.
Dynamic RAM Refresh Operation
1.
Refresh Cycle insertion is stopped when the CPU is in
the following states:
a.
During RESET
b.
When the bus is released in response to
BUSREQ.
c.
During SLEEP mode.
d.
During WAIT states.
2.
Refresh cycles are suppressed when the bus is
released in response to BUSREQ. However, the
refresh timer continues to operate. Thus, the time at
which the first refresh cycle occurs after the
Z80180/Z8S180/Z8L180 re-acquires the bus depends
on the refresh timer and has no timing relationship with
the bus exchange.
3.
Refresh cycles are suppressed during SLEEP mode.
If a refresh cycle is requested during SLEEP mode,
the refresh cycle request is internally “l(fā)atched” (until
replaced with the next refresh request). The “l(fā)atched”
refresh cycle is inserted at the end of the first machine
cycle after SLEEP mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and has no relationship
with the exit from SLEEP mode.
4.
The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of the number of “missed” refresh
requests, each refresh bus cycle will use a refresh
address incremented by one from that of the previous
refresh bus cycles.
MMU COMMON BASE REGISTER
Mnemonic CBR
Address 38
MMU Common Base Register (CBR).
CBR specifies the
base address (on 4 KB boundaries) used to generate a 20-
bit physical address for Common Area 1 accesses. All bits
of CBR are reset to 0 during RESET.
Table 14. DRAM Refresh Intervals
Insertion
Interval
10 states
20 states
40 states
80 states
Time Interval
6 MHz
1.66
μ
s
3.3
μ
s
6.6
μ
s
13.3
μ
s
CYC1
0
0
1
1
CYC0
0
1
0
1
: 10 MHz
(1.0
μ
s)*
(2.0
μ
s)*
(4.0
μ
s)*
(8.0
μ
s)*
8 MHz
(1.25
μ
s)*
(2.5
μ
s)*
(5.0
μ
s)*
(10.0
μ
s)*
4 MHz
2.5
μ
s
5.0
μ
s
10.0
μ
s
20.0
μ
s
2.5 MHz
4.0
μ
s
8.0
μ
s
16.0
μ
s
32.0
μ
s
Note:
*calculated interval
Figure 79. MMU Common Base Register (BBR: I/O Address = 38H)
Bit
CB7
CB6
R/W
CB5
7
6
5
4
3
2
1
0
CB4
CB2
CB1
CB0
R/W
CB3
R/W
R/W
R/W
R/W
R/W
R/W
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Z8S180-33VSC 制造商:Zilog Inc 功能描述:IC CPU (Z80B) SMD 8S180 PLCC68
Z8S18033VSC00TR 功能描述:IC Z180 MPU 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
Z8S18033VSG 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S18033VSG00TR 制造商:Zilog Inc 功能描述:Z8S180 Series 33 MHz 5 V Enhanced Microprocessor - PLCC - 68
Z8S2128C 制造商:STEC Inc 功能描述:128GB,ZEUS SATA SSD,14.5MM - Bulk
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