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參數(shù)資料
| 型號(hào)： | Z8S18033VSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CONN HDR INVERSE 120POS 5ROW R/A |
| 中文描述： | 8-BIT, MICROPROCESSOR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 58/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18033VSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-58
P R E L I M I N A R Y
DS971800401
DMA/WAIT CONTROL REGISTER (DCNTL)
DCNTL controls the insertion of wait states into DMAC
(and CPU) accesses of memory or I/O. Also, it defines the
Request signal for each channel as level or edge sense.
DCNTL also sets the DMA transfer mode for channel 1,
which is limited to memory to/from I/O transfers.
MWI1, MWI0: Memory Wait Insertion (bits 7-6).
Speci-
fies the number of wait states introduced into CPU or
DMAC memory access cycles. MWI1 and MWI0 are set to
1 during RESET.
I
WI1, IWI0: I/O Wait Insertion (bits 5-4).
Specifies the
number of wait states introduced into CPU or DMAC I/O
access cycles. IWI1 and IWI0 are set to 1 during RESET.
See the section on Wait-State Generation for details.
DMS1, DMS0: DMA Request Sense (bits 3-2).
DMS1
and DMS0 specify the DMA request sense for channel 0
and channel 1 respectively. When reset to 0, the input is
level sense. When set to 1, the input is edge sense. DMS1
and DMS0 are cleared to 0 during RESET.
Typically, for an input/source device, the associated DMS
bit should be programmed as 0 for level sense because
the device has a relatively long time to update its Request
signal after the DMA channel reads data from it in the first
of the two machine cycles involved in transferring a byte.
An output/destination device has much less time to update
its Request signal, after the DMA channel starts a write op-
eration to it, as the second machine cycle of the two cycles
involved in transferring a byte. With zero-wait state I/O cy-
cles, which apply only to the ASCIs, it is impossible for a
device to update its Request signal in time, and edge sens-
ing must be used.
Figure 74. DMA/WAIT Control Register (DCNTL: I/O Address = 32H)
Bit
MWI1
IWI0
7
6
5
4
3
2
1
0
R/W
R/W
DMS1 DMS0
DIM1
R/W
R/W
R/W
MWI0
IWI1
DIM0
R/W
R/W
R/W
MWI1
0
0
1
1
MWI0
0
1
0
1
Wait State
0
1
2
3
IWI1
0
0
1
1
IWI0
0
1
0
1
Wait State
0
2
3
4
DMSi
1
0
Sense
Edge Sense
Level Sense
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PDF描述 |
|---|---|
| Z8S180 | CAP 0.1UF 100V +80-20% Z5U AXIAL TR-14 |
| Z8S18006FEC | CAP 1UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006FSC | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006PEC | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| Z8S18006PSC | CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S180-33VSC | 制造商:Zilog Inc 功能描述:IC CPU (Z80B) SMD 8S180 PLCC68 |
| Z8S18033VSC00TR | 功能描述:IC Z180 MPU 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| Z8S18033VSG | 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| Z8S18033VSG00TR | 制造商:Zilog Inc 功能描述:Z8S180 Series 33 MHz 5 V Enhanced Microprocessor - PLCC - 68 |
| Z8S2128C | 制造商:STEC Inc 功能描述:128GB,ZEUS SATA SSD,14.5MM - Bulk |
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