參數(shù)資料
型號(hào): Z8S18033VSC
廠商: ZILOG INC
元件分類(lèi): 微控制器/微處理器
英文描述: CONN HDR INVERSE 120POS 5ROW R/A
中文描述: 8-BIT, MICROPROCESSOR, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 51/70頁(yè)
文件大?。?/td> 387K
代理商: Z8S18033VSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-51
1
DMA DESTINATION ADDRESS REGISTER CHANNEL 0
(DAR0: I/O Address = 23H to 25H) specifies the physical destination address for channel 0 transfers. The register con-
tains 20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 destination can
be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal for
channel 0.
DMA Destination Address Register Channel
0L
Mnemonic DAR0L
Address 23
DMA Destination Address Register Channel
0H
Mnemonic DAR0H
Address 24
DMA Destination Address Register Channel
0B
Mnemonic DAR0B
Address 25
Note:
In the R1 and Z Mask, these DMA registers are
expanded from 4 bit to 3 bits in the package version of CP-
68
Figure 58. DMA Destination Address Register
Channel 0L
Figure 59. DMA Destination Address Register
Channel 0H
Figure 60. DMA Destination Address Register
Channel 0B
A19*
A18
A17
A16
DMA Transfer
Request
DREQ0
TDR0 (ASCI0)
TDR1 (ASCI1)
Not Used
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
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