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參數(shù)資料
| 型號： | Z8S180 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CAP 0.1UF 100V +80-20% Z5U AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 21/70頁 |
| 文件大小： | 387K |
| 代理商： | Z8S180 |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-21
1
external master during STANDBY mode, when the BREXT
bit in the CPU Control Register (CCR5) is 1.
As described previously for SLEEP and IDLE modes,
when a Z80180/Z8S180/Z8L180 leaves STANDBY mode
due to NMI Low, or when it leaves STANDBY mode due to
an enabled INTO-2 low when the IEF, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
SLP instruction. If the Z80180/Z8S180/Z8L180 leaves
STANDBY mode due to an external interrupt request that's
enabled in the INT/TRAP Control Register, but the IEF, bit
is 0 due to a DI instruction, the processor restarts by exe-
cuting the instruction(s) following the SLP instruction. If
INT0, or INT1 or 2 goes inactive before the end of the clock
stabilization delay, the Z80180/Z8S180/Z8L180 stays in
STANDBY mode.
Figure 17 shows the timing for leaving STANDBY mode
due
to
an
interrupt
request.
Z80180/Z8S180/Z8L180 takes either 64 or 217 (131,072)
clocks to restart, depending on the CCR3 bit.
Note
that
the
While the Z80180/Z8S180/Z8L180 is in STANDBY mode,
it will grant the bus to an external master if the BREXT bit
(CCR5) is 1. Figure 18 shows the timing of this sequence.
Note that the part takes 64 or 217 (131,072) clock cycles
to grant the bus depending on the CCR3 bit.
The latter (non-Quick-Recovery) case may be prohibitive
for many “demand driven” external masters. If so, QUICK
RECOVERY or IDLE mode can be used.
Figure 17. Z80180/Z8S180/Z8L180 STANDBY Mode Exit due to External Interrupt
φ
T
1
T
2
T
4
NMI
or
A
19
-A
0
HALT
M1
Opcode Fetch or Interrupt
Acknowledge Cycle
FFFFFH
STANDBY Mode
T
3
2
17
or 64 Cycle Delay from INTi Asserted
INTi
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| Z8S18006FEC | CAP 1UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006FSC | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006PEC | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| Z8S18006PSC | CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE |
| Z90102 | CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S18000ZCO | 功能描述:開發(fā)板和工具包 - 其他處理器 Z8S180 App Board RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| Z8S18000ZEM | 功能描述:仿真器/模擬器 Z8S180 Emulator Kit RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| Z8S18006FEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006PEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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