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參數(shù)資料
| 型號(hào)： | Z8S180 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CAP 0.1UF 100V +80-20% Z5U AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 64/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S180 |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-64
P R E L I M I N A R Y
DS971800401
OPERATION MODE CONTROL REGISTER
Mnemonic OMCR
Address 3E
The Z80180/Z8S180/Z8L180 is descended from two dif-
ferent “ancestor” processors, Zilog's original Z80 and the
Hitachi 64180. The Operating Mode Control Register (OM-
CR) can be programmed to select between certain differ-
ences between the Z80 and the 64180.
M1E (M1 Enable).
This bit controls the M1 output and is
set to a 1 during reset.
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetch-
ing an RETI from zero-wait-state memory will use three
clock machine cycles which are not fully Z80-timing com-
patible but are compatible with the on-chip CTCs.
When MIE=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruc-
tion once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that in-
clude driving M1 Low. This may be needed by some exter-
nal Z80 peripherals to properly decode the RETI instruc-
tion.I/O Control Register (ICR).
ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode (Figure 84).
Figure 82. Operating Control Register
(OMCR: I/O Address = 3EH)
D7
Reserved
D6 D5 --
IOC (R/W)
M1TE (W)
M1E (R/W)
--
--
--
--
Figure 83. RETI Instruction Sequence with MIE=0
Figure 84. I/O Control Register (ICR: I/O Address = 3FH)
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
T
I
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
A
0
-A
18
(A
19
)
φ
D
0
-D
7
PC
PC+1
PC
PC+1
EDH
4DH
EDH
4DH
MREQ
M1
RD
ST
IOA7
IOA6
--
--
--
--
IOSTP
Bit
7
6
5
4
3
2
1
0
--
R/W
R/W
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z8S18006FEC | CAP 1UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006FSC | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| Z8S18006PEC | CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14 |
| Z8S18006PSC | CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE |
| Z90102 | CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S18000ZCO | 功能描述:開發(fā)板和工具包 - 其他處理器 Z8S180 App Board RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| Z8S18000ZEM | 功能描述:仿真器/模擬器 Z8S180 Emulator Kit RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評(píng)估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| Z8S18006FEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006PEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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