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參數(shù)資料
| 型號： | ZL30410QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CONN SOCKET R/A 4R0W 24POS SLD |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 400K |
| 代理商： | ZL30410QCC |
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ZL30410
Data Sheet
14
Zarlink Semiconductor Inc.
2.5 JTAG Interface
The ZL30410 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990,
which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made
up of four basic elements, Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers
(TDR) and all these elements are implemented on the ZL30410.
Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the
information required for a JTAG test system to access the ZL30410's boundary scan circuitry. The file is available
for download from the Zarlink Semiconductor web site: www.zarlink.com.
3.0 Control Interface
The ZL30410 has a built-in simple control interface that makes it suitable for application that can provide only a
limited amount of supervision. This allows for building multi-service line cards without extensive programming. The
complete set of control and status pins is shown in Figure 6 - Control Interface on page 14.
Figure 6 - Control Interface
3.1 Control Pins
The ZL30410 has five dedicated control pins for selecting modes of operation and activating different functions.
These pins are listed below:
MS2 and MS1 pins
:
Mode Select
: The MS2 (pin 19) and MS1 (pin 18) inputs select the PLL mode of operation.
See Table 1 for details. The logic level at these inputs is sampled by the rising edge of the F8o frame pulse.
MS2
MS1
Mode of Operation
0
0
Normal mode
0
1
Holdover mode
1
0
Free-run
1
1
Reserved
Table 1 - Operating Modes and States
C
O
N
T
R
O
L
S
T
A
T
U
S
Input Pins
LOCK
HOLDOVER
PRIOR
SECOR
MS2
MS1
FCS
RefSel
RefAlign
Output Pins
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