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參數(shù)資料
| 型號： | ZL30410QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CONN SOCKET R/A 4R0W 24POS SLD |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 400K |
| 代理商： | ZL30410QCC |
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ZL30410
Data Sheet
6
Zarlink Semiconductor Inc.
36
Tclk
IEEE1149.1a Test Clock Signal
(5 V tolerant input). Input clock for the JTAG
test logic. If not used, this pin should be pulled up to VDD.
37
Trst
IEEE1149.1a Reset Signal
(3.3 V input). Asynchronous reset for the JTAG
TAP controller. This pin should be pulsed low on power-up to ensure that the
device is in the normal functional state. This pin is internally pulled up to VDD.
If this pin is not used then it should be connected to GND.
38
Tdi
IEEE1149.1a Test Data Input
(3.3 V input). Input for JTAG serial test
instructions and data. This pin is internally pulled up to VDD. If not used, this
pin should be left unconnected.
39
NC
No internal bonding Connection.
Leave unconnected.
40
NC
No internal bonding Connection.
Leave unconnected.
41
PRIOR
Primary Reference Out of Range
(Output). Logic high at this pin indicates
that the Primary Reference is off the PLL centre frequency by more than
±12ppm. See PRIOR pin description in Section 3.2 on page 15 for details.
42
C1.5o
Clock 1.544 MHz
(CMOS tristate output). This output provides a 1.544 MHz
DS1 rate clock.
43
C6o
Clock 6.312 MHz
(CMOS tristate output). This output provides a 6.312 MHz
DS2 rate clock.
44
IC
Internal Connection
. Connect this pin to Ground.
45
GND
Ground
.
46
C19o
Clock 19.44 MHz
(CMOS tristate output). This output provides a 19.44 MHz
clock.
47
RefSel
Reference Source Select
(Input). A logic low selects the PRI (primary)
reference source as the input reference signal and logic high selects the SEC
(secondary) input. The logic level at this input is sampled at the rising edge of
F8o. This pin is internally pulled down to GND.
48
RefAlign
Reference Alignment
(Input). In Hardware Control pulling this pin low for 250
μs initiates phase realignment between the input reference and the generated
output clocks. See Section 2.2.4 on page 9 for details. This pin should never
be tied low permanently. Internally this pin is pulled down to GND.
49
VDD
Positive Power Supply
.
50
NC
No internal bonding Connection.
Leave unconnected.
51
C20i
Clock 20 MHz
(5 V tolerant input). This pin is the input for the 20MHz Master
Clock Oscillator. The clock oscillator should be connected directly (not AC
coupled) to the C20i input and it must supply clock with duty cycle that is not
worse than 40/60%.
52
GND
Digital Ground
.
Pin Description (continued)
Pin #
Name
Description
相關PDF資料 |
PDF描述 |
|---|---|
| ZL30414 | SONET/SDH Clock Multiplier PLL |
| ZL30414QGC | SONET/SDH Clock Multiplier PLL |
| ZL30414QGC1 | SONET/SDH Clock Multiplier PLL |
| ZL30415 | SONET/SDH Clock Multiplier PLL |
| ZL30415GGC | SONET/SDH Clock Multiplier PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30410QCC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30410QCG1 | 制造商:Microsemi Corporation 功能描述:IC SONET/SDH NETWORK ELEMENT PLL 制造商:Microsemi Corporation 功能描述:LEAD FREE SONET/SDH NETWORK ELEMENT PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH/PDH 80LQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH/PDH 80LQFP |
| ZL30414 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30414QGC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30414QGC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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