參數(shù)資料
型號(hào)： ZL38002
廠(chǎng)商： Zarlink Semiconductor Inc.
英文描述： Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述： 低電壓聲回波抵消與降噪
文件頁(yè)數(shù)： 13/47頁(yè)
文件大?。?/td> 440K
代理商： ZL38002
ZL38002
Data Sheet
13
Zarlink Semiconductor Inc.
Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4)
2.2 SSI Operation
The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock
(BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2’s
complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the
next.
PORT1
Rin/Sout
ST-BUS/GCI Mode
Selection
PORT2
Sin/Rout
Enable Pins
Enable Pins
MD1
ENA1
MD2
ENA2
0
0
Mode 1. 8 bit companded PCM I/O on timeslot 0
0
0
0
1
Mode 2. 8 bit companded PCM I/O on timeslot 2.
0
1
1
0
Mode 3. 8 bit companded PCM I/O on timeslot 2.
Includes D & C channel bypass in timeslots 0 & 1.
1
0
1
1
Mode 4. 16-bit 2’s complement linear PCM I/O on
timeslots 0 & 1.
1
1
Table 2 - ST-BUS & GCI Mode Select
C4i
F0i (stbus)
Rin
Sout
7 6 5 4 3 2 1 0
Sin
Rout
PORT1
PORT2
S1413 12 1110 9 8
ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and
PORT2 need not necessarily both be in mode 4.
outputs = High impedance
inputs = don’t care
7 6 5 4 3 2 1 0
S1413 12 1110 9 8
7 6 5 4 3 2 1 0
S1413 12 1110 9 8
7 6 5 4 3 2 1 0
S1413 12 1110 9 8
F0i (GCI)
start of frame (stbus & GCI)
EC
EC
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