參數(shù)資料
型號(hào)： ZL38002
廠商： Zarlink Semiconductor Inc.
英文描述： Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述： 低電壓聲回波抵消與降噪
文件頁(yè)數(shù)： 18/47頁(yè)
文件大?。?/td> 440K
代理商： ZL38002
ZL38002
Data Sheet
18
Zarlink Semiconductor Inc.
To begin execution from the RAM once the program has been loaded, the bootload mode must be disabled (BOOT
bit,
C
2
=0) and execution from RAM enabled (RAM_ROMb bit,
C
3
=1) by setting the appropriate bits in the BRC
register. During the bootload process, however, ROM program execution (RAM_ROMb bit,
C
3
=0) should be
selected. See Table 5 for the effect of the BRC register settings on Microport accesses and on program execution.
Following program loading and enabling of execution from RAM, it is recommended that the user set the software
reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of
the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as
the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.)
To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register
(see Register Summary). This register reflects the identity code (revision number) of the last program to run register
initialization (which follows a software or hardware reset.)
Figure 8 - Serial Microport Timing for Intel Mode 0
R/W
A
0
A
1
A
2
A
3
A
4
A
5
X
COMMAND/ADDRESS
DATA INPUT/OUTPUT
DATA 1
SCLK
CS
D
D
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38002.
The ZL38002:
outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
latches receive data on the rising edge of SCLK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL38002_07 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Echo Canceller for Hands Free Communication
ZL38002DGA1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002DGB1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low-Voltage Acoustic Echo Canceller With Noise Reduction
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