參數(shù)資料
型號(hào)： ZL38002
廠商： Zarlink Semiconductor Inc.
英文描述： Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述： 低電壓聲回波抵消與降噪
文件頁數(shù)： 15/47頁
文件大?。?/td> 440K
代理商： ZL38002
ZL38002
Data Sheet
15
Zarlink Semiconductor Inc.
2.4 Linear PCM
The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T
G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2’s complement linear code which
gives a maximum signal level of +15 dBm0.
2.5 Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI
(BCLK) interface.
In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen
clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can
be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin)
are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge
of BCLK. See Figure 13.
In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.
2.6 Master Clock (MCLK)
A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the
8 KHz frame.
3.0 Microport
The serial microport provides access to all ZL38002 internal read and write registers, plus write-only access to the
bootloadable program RAM (see next section for bootload description). This microport is compatible with Intel
MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Microwire specifications. The
microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a
synchronous data clock pin (SCLK).
The ZL38002 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National
specifications. The microport dynamically senses the state of the SCLK pin each time the CS pin becomes active
(i.e., high to low transition). If the SCLK pin is high during a CS activation, then the Intel mode 0 timing is assumed.
In this case the DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally
disconnected. If SCLK is low during a CS activation, then Motorola/National timing is assumed and DATA1 is
defined as the data transmit pin while DATA2 becomes the data receive pin. The ZL38002 supports Motorola half-
PCM Code
Sign-Magnitude
FORMAT=0
ITU-T (G.711)
FORMAT=1
μ
/A-LAW
LAW = 0 or 1
μ
-LAW
LAW = 0
A-LAW
LAW =1
+ Full Scale
1111 1111
1000 0000
1010 1010
+ Zero
1000 0000
1111 1111
1101 0101
- Zero
0000 0000
0111 1111
0101 0101
- Full Scale
0111 1111
0000 0000
0010 1010
Table 4 - Companded PCM
相關(guān)PDF資料
PDF描述
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ZL38002DGB1 Low-Voltage Acoustic Echo Canceller With Noise Reduction
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL38002_07 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Echo Canceller for Hands Free Communication
ZL38002DGA1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002DGB1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002DGE1 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 36QSOP /B - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCELLER AEC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCELLER AEC 36SSOP
ZL38002DGF1 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 36QSOP /B - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCELLER AEC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCELLER AEC 36SSOP
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