參數(shù)資料
型號(hào)： ZL38002
廠商： Zarlink Semiconductor Inc.
英文描述： Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述： 低電壓聲回波抵消與降噪
文件頁(yè)數(shù)： 22/47頁(yè)
文件大?。?/td> 440K
代理商： ZL38002
ZL38002
Data Sheet
22
Zarlink Semiconductor Inc.
6.0 Register Definitions
Bit
Name
Description
7
LIMIT
When high, Rin and Sin signals are limited to 0.25 in amplitude.
When low, no limit is imposed on the inputs.
6
MUTE_R
When high, the Rin path is muted to quiet code (after the NLP) and when low
the Rin path is not muted.
5
MUTE_S
When high, the Sin path is muted to quiet code (after the NLP) and when low
the Sin path is not muted.
4
BYPASS
When high, the Send and Receive paths are transparently by-passed from
input to output and when low the Send and Receive paths are not bypassed.
3
NB-
When high, Narrowband signal detectors in Rin and Sin paths are disabled
and when low the signal detectors are enabled.
2
AGC-
When high, AGC is disabled and when low AGC is enabled.
1
AH-
When high, the Howling detector is disabled and when low the Howling
detector is enabled.
0
RESET
When high, the power initialization routine is executed presetting all registers
to default values.
This bit automatically clears itself to’0’ when reset is complete.
Register Table 1 - Main Control Register 1 (MC1)
Bit
Name
Description
7
SHFT
When high and in 16-bit linear mode, this bit enables shift right by 2 on inputs
Sin, Rin, and shift left by 2 on outputs Sout, Rout, for codec. If not in 16-bit
linear mode for
both I/O port
s, this bit is ignored.
When low, =default, no shift.
6
Reserved
Reserved: Must be set to low
5
Reserved
Reserved: Must be set to low
Register Table 2 - Main Control Register 2 (MC2)
Read/Write Page 0, Address: 00
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
LIMIT
MUTE_R
MUTE_S
BYPASS
NB-
AGC-
AH-
RESET
Read/Write Address: 01
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
SHFT
Reserved
Reserved
NRdis
NSUP3
NSUP2
NSUP1
NSUP0
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