參數(shù)資料
型號(hào)： ZL50012
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 512-ch Digital Switch
中文描述： 靈活的512通道數(shù)字開關(guān)
文件頁數(shù)： 19/65頁
文件大?。?/td> 1145K
代理商： ZL50012
ZL50012
Data Sheet
22
Zarlink Semiconductor Inc.
2.3 Serial Data Input Delay and Serial Data Output Offset
Various registers are provided to adjust the input and output delays for every input and every output data stream.
The input and output channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 channel(s) for the 2.048 Mb/s,
4.096 Mb/s and 8.192 Mb/s modes respectively.
The input and output bit delay can vary from 0 to 7 bits. The fractional input bit delay can vary from 1/4, 1/2, 3/4 to
4/4 bit. The fractional output bit advancement can vary from 0, 1/4, 1/2 to 3/4 bit.
2.3.1 Input Channel Delay Programming
This feature allows each input stream to have a different input frame boundary with respect to the input frame
boundary defined by the FPi and CKi. By default, all input streams have channel delay of zero such that Ch0 is the
first channel that appears after the input frame boundary (see Figure 15).
The input channel delay programming is enabled by setting Bit 3 to 9 in the Stream Input Delay Register (SIDR).
The input channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
modes respectively.
Figure 15 - Input Channel Delay Timing Diagram
2.3.2 Input Bit Delay Programming
In addition to the input channel delay programming, the input bit delay programming feature provides users with
more flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on
PCM highways which are connected to the switch matrix cards.
By default, all input streams have zero bit delay such that Bit 7 is the first bit that appears after the input frame
boundary, see Figure 16. The input delay is enabled by Bit 0 to 2 in the Stream Input Delay Registers (SIDR). The
input bit delay can vary from 0 to 7 bits.
FPi
7
2
3
4
5
6
1 0
Channel Delay = 0
Ch 0
7
2
3
4
5
6
1 0
Ch 1
2
3
1 0
7
2
3
4
5
6
1 0
Last Channel
2
3
4
5
6
1 0
Last Channel -1
7 6
7
2
3
4
5
6
1 0
Channel Delay = 1
Last Channel
7
2
3
4
5
6
1 0
Ch 0
2
3
1 0
7
2
3
4
5
6
1 0
Last Channel -1
2
3
4
5
6
1 0
Last Channel -2
7 6
7
2
3
4
5
6
1 0
Channel Delay = 2
Last Channel -1
7
2
3
4
5
6
1 0
Last Channel
2
3
1 0
7
2
3
4
5
6
1 0
Last Channel -2
2
3
4
5
6
1 0
Ch0
7 6
(Default)
Delay = 1
Delay = 2
7
STi
X
STi
X
STi
X
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Input Frame Boundary
Note:
X
= 0 to 15
相關(guān)PDF資料
PDF描述
ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50012/GDC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 144LBGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 512CH 144LBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 512CH 144LBGA
ZL50012/QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 160LQFP - Trays
ZL50012_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 512-ch Digital Switch
ZL50012GDC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 512-ch Digital Switch
ZL50012GDG2 制造商:Microsemi Corporation 功能描述:Switch Fabric 256 x 256 3.3V 144-Pin LBGA Tray 制造商:Microsemi Corporation 功能描述:TDM SWITCH 512X512 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 144LBGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 512CH 144LBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 512CH 144LBGA
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