參數(shù)資料
型號(hào)： ZL50012
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 512-ch Digital Switch
中文描述： 靈活的512通道數(shù)字開關(guān)
文件頁數(shù)： 35/65頁
文件大?。?/td> 1145K
代理商： ZL50012
ZL50012
Data Sheet
38
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 12
Unused
Reserved.
In normal functional mode, these bits MUST be set to zero.
11
CKINP
ST Bus Clock Input (CKi) Polarity.
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
10
FPINP
Frame Pulse Input (FPi) Polarity.
When this bit is low, the input frame pulse FPi should have the negative frame pulse
format. When this bit is high, the input frame pulse FPi should have the positive frame
pulse format.
9
CK2P
ST Bus Clock Output (CKo2) Polarity.
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
8
FP2P
Frame Pulse Output (FPo2) Polarity.
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
7
CK1P
ST Bus Clock Output (CKo1) Polarity.
When this bit is low, the output clock CKo1 falling edge aligns with the frame bound-
ary. When this bit is high, the output clock CKo1 rising edge aligns with the frame
boundary.
6
FP1P
Frame Pulse Output (FPo1) Polarity.
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.
5
CK0P
ST Bus Clock Output (CKo0) Polarity.
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.
4
FP0P
Frame Pulse Output (FPo0) Polarity.
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.
3 - 1
BPD2 - 0
Block Programming Data:
These bits refer to the value to be loaded into the connec-
tion memory. Whenever the memory block programming feature is activated. After the
MBPE bit in the control register is set to high and the MBPS bit is set to high, the con-
tents of the bits BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory.
Bit 3 to Bit 11 of the connection memory are zeroed.
Table 16 - Internal Mode Selection (IMS) Register Bits
External Read/Write Address: 001
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
CKINP
FPINP
CK2P
FP2P
CK1P
FP1P
CK0P
FP0P
BPD
2
BPD
1
BPD
0
MBPS
相關(guān)PDF資料
PDF描述
ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50012/GDC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 144LBGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 512CH 144LBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 512CH 144LBGA
ZL50012/QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 160LQFP - Trays
ZL50012_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 512-ch Digital Switch
ZL50012GDC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 512-ch Digital Switch
ZL50012GDG2 制造商:Microsemi Corporation 功能描述:Switch Fabric 256 x 256 3.3V 144-Pin LBGA Tray 制造商:Microsemi Corporation 功能描述:TDM SWITCH 512X512 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 3.3V 144LBGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 512CH 144LBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 512CH 144LBGA
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