參數(shù)資料
型號: ZL50012
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 512-ch Digital Switch
中文描述: 靈活的512通道數(shù)字開關(guān)
文件頁數(shù): 24/65頁
文件大?。?/td> 1145K
代理商: ZL50012
ZL50012
Data Sheet
27
Zarlink Semiconductor Inc.
By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (
T
) is:
T = 2 frames + (m-n)
. Figure 21 shows the throughput delay when the input Ch0 is switched to the output Ch0.
Figure 21 - Data Throughput Delay when input and output channel delay are disabled for Input
Ch0 switched to Output Ch0
When the input channel delay is enabled and the output channel delay is disabled, the data throughput delay is:
T =
3 frames -
α
+ (m-n)
. Figure 22 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Figure 22 - Data Throughput Delay when input channel delay is enabled and output channel
delay is disabled for Input Ch0 switched to Output Ch0
When the input channel delay is disabled and the output channel delay is enabled, the throughput delay is:
T = 2
frames +
β
+ (m-n)
. Figure 23 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel
delay is enabled for Input Ch0 switch to Output Ch0
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Serial Input Data
(No Delay)
Serial Output Data
(No Delay)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + 0
Frame
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Serial Input Data
(
α
= 1)
Serial Output Data
(No Delay)
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Serial Input Data
(
α
> 1)
Frame N-1 Data
Frame N
Input Channel Delay (from 1 to max# of channels, programmed by the STIN#CD6-0 bit)
3 Frames -
α + 0
3 Frames - 1 channel + 0
Frame
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Serial Input
(No Delay)
Serial Output Data
(
β
> 1)
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N
Serial Output Data
(
β
= 1)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + 1 + 0
Output Channel Delay:(from 1 to max# of channels,
programmed by the STO#CD6-0 bit)
2 Frames +
β + 0
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