參數(shù)資料
型號: ZL50019GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 29/115頁
文件大?。?/td> 866K
代理商: ZL50019GAC
ZL50019
Data Sheet
29
Zarlink Semiconductor Inc.
8.2 Input Bit Sampling Point Programming
In addition to the input bit delay feature, the ZL50019 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input
streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the
sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default
sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
Figure 14 - Input Bit Sampling Point Programming
FPi
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
Channel 0
Last Channel
Sampling Point = 1/4 Bit
STi[n]
STIN[n]SMP1-0 = 10
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 00
(16 Mbps - Default)
Channel 0
6
Last Channel
1
Sampling Point = 1/2 Bit
STi[n]
STIN[n]SMP1-0 = 00
(2, 4 or 8 Mbps -
Default)
Channel 0
6
Last Channel
1
Sampling Point = 3/4 Bit
0
7
2
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
STi[n]
STIN[n]SMP1-0 = 11
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 10
(16 Mbps)
Channel 0
Last Channel
Sampling Point = 4/4 Bit
5
1
0
7
6
5
0
7
5
1
0
7
6
2
5
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