參數(shù)資料
型號: ZL50019GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 64/115頁
文件大小: 866K
代理商: ZL50019GAC
ZL50019
Data Sheet
64
Zarlink Semiconductor Inc.
7
MTR
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
6 - 5
PRS1 - 0
Preferred Reference Selection Bits
These bits select the preferred reference from one of the input references.
4 - 2
PMS2 - 0
Preference Mode Selection Bits
These bits select one of the preference modes:
1 - 0
FDM1 - 0
Force DPLL Mode
These bits force the DPLL into one of the valid operation modes.
Bit
Name
Description
Table 35 - Reference Change Control Register (RCCR) Bits (continued)
External Read/Write Address: 004B
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
PRS1
PRS0
Preferred Reference Selection
0
0
REF0
0
1
REF1
1
0
REF2
1
1
REF3
PMS2
PMS1
PMS0
Preference Mode
0
0
0
No Preference
0
0
1
Preference as per the setting
of the PRS1 - 0 bits
0
1
0
Force REF0
0
1
1
Force REF1
1
0
0
Force REF2
1
0
1
Force REF3
110 - 111
Reserved
FDM1
FDM0
Operation Mode
0
0
Automatic
0
1
Normal
1
0
Holdover
1
1
Freerun
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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