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參數(shù)資料
| 型號： | ZL50019GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA256 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256 |
| 文件頁數(shù)： | 36/115頁 |
| 文件大?。?/td> | 866K |
| 代理商： | ZL50019GAC |
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ZL50019
Data Sheet
36
Zarlink Semiconductor Inc.
internal to the device and are synchronized to CKi and FPi. All specified frequencies are available on CKo[0:3] in
Multiplied Slave mode.
By default, the DPLL is disabled if the device is in Slave mode. However, the DPLL can be activated by
programming the SLV_DPLLEN bit in the Control Register. When the DPLL is enabled, CKo4, CKo5 and FPo5 will
be generated from the DPLL, while the other clocks and frame pulses will be generated based on CKi/FPi. In this
case the DPLL will be fully functional, including its capability of reference monitoring.
Note that an external oscillator is required whenever the DPLL is used.
Table 7, “ZL50019 Operating Modes” on page 36 summarizes the different modes of operation available within the
ZL50019. Each Major mode (explained below) has an associated Minor mode that is determined by setting the
relevant Input Control pins and Control Register bits (Table 16, “Control Register (CR) Bits” on page 48) indicated in
the table.
12.1 Master Mode Performance
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to
REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and
holdover functions. In this mode, STio0 - 31 are driven by a clock generated by the DPLL, which also provides all
the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2).
12.2 Divided Slave Mode Performance
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data
rate defined by CKi. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps, and
the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is not enabled, an external oscillator is
optional in Divided Slave mode.
Device
Input Pins
CR Register
Output Clock Pins
Data Pins
Operating Mode
Control
Signal
Bits
Reference Lock
Enabled
Clock Source
Major
Minor
OSC_EN
MODE_4M
[1:0]
OSCi
CKi
OPM
[1:0]
SLV_DPLLEN CKi_LP
CKo0-3
CKo4-5
CKo0-3
CKo4-5
STi
STo
Master
CKi
1
00
2 0MHz 4/8/16 M
00
X
0
Freerun, Holdover
or REF0-3
Yes
Yes
CKi*
Cko2
(DPLL)
Loopback
X
1
Cko2
Divided
Slave
4 M
1
11
20 MHz
4 M
01
1
X
CKi
REF0-3
Yes
CKi
CKo0-3
(CKi)
8/16 M
00
8/16 M
4 M
0
11
X
4 M
X0
0
X
No
8/16 M
00
8/16 M
Multiplied
Slave
4 M
1
11
20 MHz
4 M
11
1
CKi MULT REF0-3
Yes
CKo0-3
(CKi MULT)
8/16 M
00
8/16 M
4 M
0
11
X
4 M
X1
0
X
No
8/16 M
00
8/16 M
Legend:
X
Don’t care or not applicable.
Reference Lock
REF0-3 = Normal
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
* CKi must be phase aligned (edge synchronous) to CLo0-3.
Clock Source
Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
Table 7 - ZL50019 Operating Modes
Refers to what signal the output pins are locked to:
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相關(guān)代理商/技術(shù)參數(shù) |
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| ZL50019GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH RATE CONVERSION+S4E DPLL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50019QCC | 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION AND S4 - Trays |
| ZL50019QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH+CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
| ZL50020 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch |
| ZL50020GAC | 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION - Trays |
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