參數(shù)資料
型號: ZL50019GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 63/115頁
文件大?。?/td> 866K
代理商: ZL50019GAC
ZL50019
Data Sheet
63
Zarlink Semiconductor Inc.
Table 33 - Lock Detector Interval Register (LDIR) Bits
Bit
Name
Description
15 - 0
LDI15 - 0
Lock Detector Interval Bits
The binary value of these bits defines the time interval that the output phase detector
must be below the lock detect threshold to declare lock. Unsigned representation of the
LDI bits is defined in 4 ms intervals.
Bit
Name
Description
15 - 13
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
12 - 0
SRL12 - 0
Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is
±
56 ppm (’h099F/CFN = 56 ppm).
Table 34 - Slew Rate Limit Register (SRLR) Bits
Bit
Name
Description
15 - 8
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
Table 35 - Reference Change Control Register (RCCR) Bits
External Read/Write Address: 0048
H
Reset Value: 2C00
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDI
15
LDI
14
LDI
13
LDI
12
LDI
11
LDI
10
LDI
9
LDI
8
LDI
7
LDI
6
LDI
5
LDI
4
LDI
3
LDI
2
LDI
1
LDI
0
External Read/Write Address: 0049
H
Reset Value: 099F
H
(see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
SRL
12
SRL
11
SRL
10
SRL
9
SRL
8
SRL
7
SRL
6
SRL
5
SRL
4
SRL
3
SRL
2
SRL
1
SRL
0
External Read/Write Address: 004B
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
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