參數(shù)資料
型號: ZL50019GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 31/115頁
文件大?。?/td> 866K
代理商: ZL50019GAC
ZL50019
Data Sheet
31
Zarlink Semiconductor Inc.
8.4 Fractional Output Bit Advancement Programming
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.
By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.
Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
FPi
STio[n]
STo[n]FA1-0 = 00
(Default 2, 4, 8 or
16Mb/s)
Channel 0
7
Last Channel
STio[n]
STo[n]FA1-0 = 01
(2, 4 or 8 Mbps)
Channel 0
Last Channel
Fractional Bit Advancement = 1/4 Bit
6
5
2
1
0
STio[n]
STo[n]FA1-0 = 10
(2,
4
or
STo[n]FA1-0 = 01
(16 Mbps)
8Mbps)
Channel 0
Last Channel
Fractional Bit Advancement = 1/2 Bit
STio[n]
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)
Channel 0
Last Channel
Fractional Bit Advancement = 3/4 Bit
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
7
6
5
1
0
7
6
5
1
0
7
6
5
1
0
4
4
4
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