參數(shù)資料
型號(hào)： ZL50418GKC
廠商： Zarlink Semiconductor Inc.
英文描述： Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述： 管理16端口10/100平方米端口1個(gè)G以太網(wǎng)交換機(jī)
文件頁數(shù)： 22/163頁
文件大小： 2122K
代理商： ZL50418GKC
ZL50418
Data Sheet
22
Zarlink Semiconductor Inc.
4.3 Memory Requirements
To speed up searching and decrease memory latency, the external MAC address database is duplicated in both
memory banks. To support 64 K MAC address, 4 MB memory is required. When VLAN support is enabled, 512
entries of the MAC address table are used for storing the VLAN ID at VLAN Index Mapping Table.
Up to 2 K Ethernet frame buffers are supported and they will use 3 MB of memory. Each frame uses 1536 bytes.
The maximum system memory requirement is 4 MB. If less memory is desired, the configuration can scale down.
Memory Configuration
Memory Map
Figure 7 - Memory Map
Bank A
Bank B
Tag based VLAN
Frame Buffer
Max MAC Address
1 M
1 M
Disable
1 K
32 K
1 M
1 M
Enable
1 K
31.5 K
2 M
2 M
Disable
2 K
64 K
2 M
2 M
Enable
2 K
63.5 K
Table 1 - Memory Configuration
1 M Bank A
0.75 M
0.25 M
Tag based VLAN Disable
1 M Bank B
0.75 M
0.25 M
1 M Bank A
0.75 M
0.25 M -4 K
1 M Bank B
0.75 M
0.25 M-
4 K
4 K
Tag based VLAN Enable
2 M Bank A
1.5 M
0.5 M
2 M Bank B
1.5 M
0.5 M
2 M Bank A
1.5 M
0.5 M -4 K
2 M Bank B
1.5 M
0.5 M-
4 K
4 K
Tag based VLAN Enable
Frame Data Buffer (FDR) Area
MAC Address Control Table (MCT) Area
VLAN Table Area
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