參數(shù)資料
型號: ZL50418GKC
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述: 管理16端口10/100平方米端口1個G以太網(wǎng)交換機
文件頁數(shù): 95/163頁
文件大?。?/td> 2122K
代理商: ZL50418GKC
ZL50418
Data Sheet
95
Zarlink Semiconductor Inc.
W5 - QOSC45[5:0] – CREDIT_C5_G1 (CPU Address 544)
W6 - QOSC46[5:0] – CREDIT_C6_G1 (CPU Address 545)
W7 - QOSC47[5:0] – CREDIT_C7_G1 (CPU Address 546)
QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the
numbers is 1 and their sum must be 64. QOSC47 corresponds to W7, and QOSC40 corresponds to W0.
14.9.35 Classes WFQ Credit Port G2
Accessed by CPU and serial interface
W0 - QOSC48[5:0] – CREDIT_C0_G2(CPU Address 547)
[7:6]: Priority service type. Option 1 to 4
W1 - QOSC49[5:0] – CREDIT_C1_G2(CPU Address 548)
[7]: Priority service allow flow control for the ports select this parameter set.
[6]: Flow control pause best effort traffic only
W2 - QOSC50[5:0] – CREDIT_C2_G2(CPU Address 549)
W3 - QOSC51[5:0] – CREDIT_C3_G2(CPU Address 54a)
W4 - QOSC52[5:0] – CREDIT_C4_G2(CPU Address 54b)
W5 - QOSC53[5:0] – CREDIT_C5_G2(CPU Address 54c)
W6 - QOSC54[5:0] – CREDIT_C6_G2(CPU Address 54d)
W7 - QOSC55[5:0] – CREDIT_C7_G2(CPU Address 54e)
QOSC48 through QOSC55 represents the set of WFQ parameters for Gigabit port 2. The granularity of the
numbers is 1 and their sum must be 64. QOSC55 corresponds to W7 and QOSC48 corresponds to W0.
14.9.36 Class 6 Shaper Control Port G1
Accessed by CPU and serial interface
QOSC56[5:0] – TOKEN_RATE_G1 (CPU Address 54f). Programs de average rate for gigabit port 1. When equal to
0, shaper is disable. Granularity is 1.
QOSC57[7:0] – TOKEN_LIMIT_G1 (CPU Address 550). Programs the maximum counter for gigabit port 1.
Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC41 programs the peak rate for gigabit port 1.
See Programming QoS Registers Application Note for more information
14.9.37 Class 6 Shaper Control Port G2
Accessed by CPU and serial interface
QOSC58[5:0] – TOKEN_RATE_G2 (CPU Address 551). Programs de average rate for gigabit port 2. When equal
to 0, shaper is disable. Granularity is 1.
QOSC59[7:0] – TOKEN_LIMIT_G2 (CPU Address 552). Programs the maximum counter for gigabit port 2.
Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC49 programs the peak rate for gigabit port 2.
See Programming QoS Register Application Note for more information.
相關(guān)PDF資料
PDF描述
ZL60101 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60101MJD 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60102 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60102MJD 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60212 880 nm High-Performance Single-chip DUPLEX
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL51B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL56B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL5V1B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL5V6B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL60001 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:High speed 2.5 Gbps 850 nm VCSEL