參數(shù)資料
型號(hào)： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 22/81頁(yè)
文件大?。?/td> 441K
代理商： ΜPD705100
22
V830
TM
USER'S MANUAL
2.2 EXPLANATION OF PIN FUNCTIONS
This section describes the pin functions of the V830. Each state of a bus cycle regards the time between
the rise of one bus clock pulse to the rise of the next as one unit.
(1)
A2-A27 (Address Bus): tristate output
Pins from which the CPU outputs an address signal when accessing main external storage or an input/
output device. The output signal is synchronized with the rise of a bus clock pulse (BCLK) in Ta.
(2)
A28-A31/CS0-CS3 (Address Bus/Chip Select): tristate output
Pins from which the CPU outputs an address or chip select signal when accessing main external storage
or an input/output device. An address signal is output from A28-A31 if ASEL is at the high level at reset,
while a chip select signal is output if it is at the low level. These signals are output from A28-A31/CS0-
CS3 in synchronization with the rise of a clock pulse in the Ta and Tb2-Tb4 states (Ta, Tw2, and Tb2-
Tb8 states in 16-bit mode). A chip select signal is output only during a bus cycle. The areas where
the chip select output is valid are fixed statically according to the hardware.
Table 2-1. Chip Select Output vs. Address Space
Pin
Memory
I/O
Address space
CS0
o
x
FE001000H-FFFFFFFFH (Cachable area)
7E000000H-7FFFFFFFH (Uncachable area)
CS1
o
x
40000000H-4FFFFFFFH (Uncachable area)
00001000H-0FFFFFFFH (Cachable area)
CS2
o
x
50000000H-5FFFFFFFH (Uncachable area)
10000000H-1FFFFFFFH (Cachable area)
CS3
o
x
60000000H-6FFFFFFFH (Uncachable area)
20000000H-2FFFFFFFH (Cachable area)
(3)
D0-D31 (Data Bus): tristate input/output
Pins which the CPU uses to input and output read and write data when accessing main external storage
or an input/output device. During a write cycle, an output signal is synchronized with the rise of a bus
clock pulse in the Ta, Ts, Tb1-Tb8, Tw1, and Tw2 states. For details, see
Section 4.2
(for 32-bit bus
mode) and
Section 5.3
(for 16-bit bus mode).
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