參數(shù)資料
型號(hào)： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 26/81頁(yè)
文件大小： 441K
代理商： ΜPD705100
26
V830
TM
USER'S MANUAL
(17) BCLK (Bus Clock): input
Receives bus clock pulses. A bus cycle is activated each time BCLK is input. The frequency ratio for
the internal clock (CLK) and bus clock (BCLK) is specified with CMODE.
(18) CMODE (Clock Mode): input
Receives the signal specifying the frequency ratio for the external bus and the internal circuit. The signal
is sampled at the first bus clock pulse issued after RESET goes high. The frequency of the internal clock
is double that of the bus clock if CMODE is high at reset, or three times as high if CMODE is low.
CMODE must be connected to V
DD
or GND via a resistor.
(19) ASEL (Address Select): input
Receives the signal for selecting the output of A28-A31/CS0-CS3. The signal at ASEL is sampled at
the first bus clock pulse issued after RESET goes high. ASEL cannot be changed at any other timing.
A signal is output from A28-A31 if the input sampled at ASEL input is high, or from CS0-CS3 if the input
is low.
(20) RESET (Reset): input
Receives the signal for initializing the CPU. The signal is sampled at the fall of a clock pulse. It must
be held at the active level for at least 20 clock pulses.
When the input of RESET is accepted, the CPU initializes its pins and internal registers and executes
instructions starting from address FFFFFFF0H.
(21) V
DD
(Power Supply)
Pins used to supply positive power. All V
DD
pins must be connected to positive power.
(22) GND (Ground)
Ground pins. All GND pins must be connected to ground.
(23) IC1 (Internally Connected 1)
All IC1 pins must be left open.
(24) IC2 (Internally Connected 2)
Each IC2 pin must be connected to ground via a dedicated resistor.
(25) IC3 (Internally Connected 3)
Each IC3 pin must be connected to positive power via a dedicated resistor.
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