參數(shù)資料
型號： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁數(shù)： 50/81頁
文件大?。?/td> 441K
代理商： ΜPD705100
50
V830
TM
USER'S MANUAL
5.3 BUS CYCLES
Bus cycles can be classified into either single transfer or burst transfer bus cycles.
Single transfer bus cycles are used for the IN, OUT, and ST instructions, for the LD instruction when
executed on an uncachable area, and upon instruction fetches. In single transfer mode, data is read or written
in single units. Single transfer mode can be activated in either the memory space or I/O space.
Burst transfer bus cycles are used for refilling the cache after a cache miss and for executing the BILD,
BIST, BDLD, and BDST instructions. Burst transfer mode can be activated only in the memory space, but
in the I/O space. In burst transfer mode, four words (16 bytes) of data can be processed in each bus cycle,
but the low-order four bits of the source and destination addresses must be 0.
5.3.1 Bus States
The V830 handles data accesses with the bus width fixed to either 32 or 16 bits. A width is selected when
the V830 is reset. The bus width cannot be changed during operation. In 16-bit bus mode, the bus assumes
one of the states explained below:
In 16-bit bus mode, the bus cycles can assume one of 14 states. During the bus cycle for word access,
two external accesses are performed. The state always changes in sync with the bus clock. Note, however,
that it can also change at times either than changes in the bus clock.
(1) Ti state
The bus remains in the Ti state provided it does not receive a request to perform an access to a point
external to the processor. It also enters this state after exiting from the hold state (Th state). In the Ti
state, the BCYST, CSn, and other outputs are inactive. HLDRQ (input) and the interrupt request (input)
are sampled in sync with the rising edge of the bus clock.
(2) Ta state
The bus enters the Ta state at the beginning of a bus cycle. In this state, BCYST (output) is active. A
valid address is placed on the address bus at the rising edge of the bus clock. During a single write cycle,
valid data is placed on the data bus at the rising edge of the bus clock. During a burst write cycle, data
is not placed on the data bus.
Upon the termination of the Ta state, the bus enters the Ts state in single byte/halfword transfer mode,
the Tw1 state in single word transfer mode, or the Tb1 state in burst transfer mode.
(3) Ts state
The bus enters the Ts state upon the termination of a bus cycle or when the bus is forced to wait during
a single byte/halfword transfer. HLDRQ (input) is sampled at the rising edge of the bus clock during the
last Ts state. READY (input) is sampled at the rising edge of the bus clock upon the termination of the
Ts state. If the sampled READY (input) is inactive, the bus re-enters the Ts state starts.
If READY (input), sampled during a read, is active, the data on the data bus is read and the read cycle
ends. The bus then enters the Ti state.
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