參數(shù)資料
型號: μPD705100
廠商: NEC Corp.
英文描述: 32 Bit Microprocessor(32 位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 66/81頁
文件大?。?/td> 441K
代理商: ΜPD705100
66
V830
TM
USER'S MANUAL
7.2 SLEEP MODE
The V830 enters sleep mode upon the execution of a HALT instruction. On the other hand, escape from
sleep mode can be realized by a maskable interrupt, NMI, or reset operation.
In sleep mode, bus hold requests can be accepted. During bus hold, the status becomes high impedance
and no halt acknowledge status is output. At the end of bus hold, a halt acknowledge status is output in sync
with the rising edge of a bus clock pulse.
The timing in sleep mode is as shown below.
Figure 7-1. Halt Acknowledge Cycle
BCLK (input)
Note 1
Note 2
Halt acknowledge
D0-D31 (input/output)
(read time)
D0-D31 (input/output)
(write time)
CS0-CS3 (output)
READY (input)
Ta
Tb
Ti
Ti
Ti
Ti
Ti
Ti
Ti
Ti
Ti
Ta
Tb
Note 3
Notes 1.
A2-A27 (output), BE0-BE3 (output)
2.
ST0-ST3, R/W
3.
If no chip select function is used, A28-A31 are output to CS0-CS3.
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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