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| 型號(hào)： | μPD750100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Single Chip Microcontrollers(32位單片微控制器) |
| 中文描述： | 32位單片機(jī)微控制器（32位單片微控制器） |
| 文件頁數(shù)： | 17/66頁 |
| 文件大?。?/td> | 417K |
| 代理商： | ΜPD750100 |
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μ
PD705100
17
5. INTERRUPTS
V830 interrupts include maskable interrupts, nonmaskable interrupts, and reset operations.
5.1 Maskable Interrupts
Maskable interrupt requests are themselves denoted by INT, and their interrupt levels by INTV0 to INTV3.
The following lists pin states and the corresponding interrupt levels.
Table 5-1. Interrupt Levels
Interrupt level
INTV3
INTV2
INTV1
INTV0
15
0
0
0
0
14
0
0
0
1
13
0
0
1
0
12
0
0
1
1
11
0
1
0
0
10
0
1
0
1
9
0
1
1
0
8
0
1
1
1
7
1
0
0
0
6
1
0
0
1
5
1
0
1
0
4
1
0
1
1
3
1
1
0
0
2
1
1
0
1
1
1
1
1
0
0
1
1
1
1
INT and INTV0 to INTV3 are level inputs. The V830 samples an INT at the rising edge of a bus clock
pulse. INT and INTV0 to INTV3 should be held at the active level until the V830 accepts the interrupt request and
posts to a peripheral, by software, notification of the acceptance of the interrupt request. Although a change to a higher
interrupt level is possible, the timing at which an interrupt request is detected cannot then be posted to peripheral.
Hence, an interrupt request made before such a change may be accepted. If the interrupt request input (INT, INTV0-
INTV3) fails to satisfy the setup time requirement for the bus clock pulse, the interrupt request will be detected at the
rising edge of the next bus clock pulse.
Upon accepting an interrupt request, the V830 jumps to a fixed address to start interrupt handling. The target
address of the jump is set to FE0000n0H (built-in RAM) or FFFFFEn0H (external memory), where n is the interrupt
level, either of which may be specified with the IHA bit of the system register, HCCW.
Caution Interrupt level 15 is reserved for use by development tools (in-circuit emulator, ROM emulator,
etc). If the user uses interrupt level 15, those development tools may fail to operate.
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