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參數(shù)資料
| 型號(hào)： | μPD750100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Single Chip Microcontrollers(32位單片微控制器) |
| 中文描述： | 32位單片機(jī)微控制器（32位單片微控制器） |
| 文件頁(yè)數(shù)： | 18/66頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | ΜPD750100 |
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μ
PD705100
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5.2 Nonmaskable Interrupts
The V830 samples an NMI at the rising edge of a bus clock pulse. When the NMI changes from the high to low
level, an interrupt request is detected. Once a nonmaskable interrupt request has been detected, the NMI can
subsequently be deactivated at any time because the NMI is detected at the falling edge. An interrupt request thus
detected is retained in the CPU until the CPU starts interrupt handling.
Upon accepting a nonmaskable interrupt, the V830 jumps to the fixed address (FFFFFFD0H). If another
nonmaskable interrupt is issued during nonmaskable interrupt handling (the NP bit of PSW is set to1), it is retained
in the processor. If, however, another nonmaskable interrupt request is issued during clearing of the latch circuit by
internal processing after the start of nonmaskable interrupt handling, it is not retained in the processor.
5.3 Reset
The V830 can be reset by inputting a low-level signal of 20 or more clock pulses to RESET. After the V830 has
been reset, the CPU starts program execution from address FFFFFFF0H.
If RESET is driven high, the CPU starts instruction fetching from the reset address.
Immediately after power-on or in the stop-mode state, the active pulse width of the RESET should be determined
by adding the PLL oscillation settling time to the active level of 20 clock pulses.
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