參數(shù)資料
型號(hào)： μPD750100
廠商： NEC Corp.
英文描述： 32 Bit Single Chip Microcontrollers(32位單片微控制器)
中文描述： 32位單片機(jī)微控制器（32位單片微控制器）
文件頁數(shù)： 41/66頁
文件大?。?/td> 417K
代理商： ΜPD750100
μ
PD705100
41
12. INTERRUPTS AND EXCEPTIONS
Interrupts are events which occur independently of program execution. They are classified into maskable and
nonmaskable interrupts. In contrast, exceptions are events which are directly related to program execution. Interrupts
and exceptions do not differ greatly in their control flow, but interrupts are assigned higher handling priorities than
exceptions. Fatal exceptions, however, are assigned higher priorities than interrupts.
Under the V830 architecture, the following interrupts and exceptions may occur. When an exception, maskable
interrupt, or nonmaskable interrupt occurs, control is passed to a handler at an address which is predetermined a given
cause. The cause of an exception can be identified by means of the exception code stored in the ECR (Exception
Cause Register). The pertinent handler analyzes the contents of the ECR so that it can handle the exception or interrupt
appropriately.
Table 12-1. Exception/Interrupt Source Codes
Exception/interrupt
Category
Exception code
ECR
Note 1
Handler
address
Note1
Return PC
Reset
Interrupt
FFF0H
FFFFFFF0H
Indefinite
Fatal exception
Exception
-
FFFFFFE0H
current PC
NMI
Interrupt
FFD0H
FFFFFFD0H
next PC
Double exception
Exception
Note 2
FFFFFFD0H
current PC
TRAP instruction (parameter 0
×
1n)
Exception
FFBnH
FFFFFFB0H
next PC
TRAP instruction (parameter 0
×
0n)
Exception
FFAnH
FFFFFFA0H
next PC
Invalid operation code
Exception
FF90H
FFFFFF90H
current PC
Division by zero
Exception
FF80H
FFFFFF80H
current PC
Interrupt level n (n = 0-15)
HWCC.IHA = 0
Interrupt
FEn0H
FFFFFEn0H
next PC
HWCC.IHA = 1
FE0000n0H
Notes 1.
Level n is represented by a hexadecimal number (n = 0-F).
2.
Exception code of the exception which caused the double exception
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