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參數(shù)資料
| 型號： | μPD750100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Single Chip Microcontrollers(32位單片微控制器) |
| 中文描述： | 32位單片機(jī)微控制器（32位單片微控制器） |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 417K |
| 代理商： | ΜPD750100 |
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μ
PD705100
35
Instruction
Operand(s)
Format
CY
OV
S
Z
Function
JAL
disp26
IV
-
-
-
-
Jump and link. The sum of the current PC
and 4 is written into r31. disp26, sign-extended
to a word, is added to the PC and the sum is
set to the PC for control transfer. Bit 0 of
disp26 is masked.
JMP
[reg1]
I
-
-
-
-
Indirect unconditional branch via register.
Control is passed to the address designated by
reg1. Bit 0 of the address is masked to 0.
JR
disp26
IV
-
-
-
-
Unconditional branch. disp26, sign-extended to
a word, is added to the current PC and control
is passed to the address specified by that sum.
Bit 0 of disp26 is masked to 0.
LD.B
disp16[reg1],
reg2
VI
-
-
-
-
Byte load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A byte of data is read from the
produced address, sign-extended to a word,
then written into reg2.
LD.H
disp16[reg1],
reg2
VI
-
-
-
-
Halfword load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A halfword of data is read from the
produced address, sign-extended to a word,
then written into reg2. Bit 0 of the unsigned
32-bit address is masked to 0.
LD.W
disp16[reg1],
reg2
VI
-
-
-
-
Word load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A word of data is read from the
produced address, then written into reg2. Bits 0
and 1 of the unsigned 32-bit address are
masked to 0.
LDSR
reg2, regID
II
Load into system register. The contents of
reg2 are set in the system register identified by
the system register number (regID).
MAC3
reg1, reg2,
reg3
VIII
-
-
-
-
Saturatable operation on signed 32-bit operands.
reg1 and reg2 are multiplied together as signed
integers and the product is added to reg3.
[If no overflow has occurred:]
The result is stored in reg3.
[If an overflow has occurred:]
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
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