OP7100
Memory, I/O Map, and Interrupt Vectors
107
Power-Failure Interrupts
The INT1 line is connected to the power-failure output of the ADM691
supervisor. A power-failure interrupt occurs when PFI falls to 1.25 V ±
0.05 V. This advanced warning allows the program to perform some
emergency processing before an unwanted power-down occurs.
The following example shows how to handle a power-failure interrupt.
#INT_VEC INT1_VEC power_fail_isr
interrupt power_fail_isr(){
IRES(ITC,1); // clear bit 1 of ITC and disable /INT1
body of interrupt routine
}
You also need to add the following line to main().
ISET(ITC,1)
// enables /INT1
Interrupt Priorities
Table C-6 lists the interrupt priorities.
Table C-6. Interrupt Priorities
Interrupt Priorities
(Highest Priority)
Trap (illegal instruction)
NMI (nonmaskable interrupt)
INT 0 (maskable interrupts, Level 0; three modes)
INT 1 (maskable interrupts, Level 1; PLCBus
attention line interrupt)
INT 2 (maskable interrupts, Level 2)
PRT Timer Channel 0
PRT Timer Channel 1
DMA Channel 0
DMA Channel 1
Z180 Serial Port 0
(Lowest Priority)
Z180 Serial Port 1