A polling driver tests the ready flags (TDRE and RDRF) until a ready con" />
參數(shù)資料
型號(hào)： 20-101-0732
廠商： Rabbit Semiconductor
文件頁數(shù)： 66/126頁
文件大?。?/td> 0K
描述： INTERFACE SMART SCREEN OP7100
標(biāo)準(zhǔn)包裝： 1
系列： SBC
模塊/板類型： 單板計(jì)算機(jī)模塊
適用于相關(guān)產(chǎn)品： OP7100
其它名稱： 20-101-732
20-101-732-ND
OP7100
44
Hardware
The serial ports can be polled or interrupt-driven.
A polling driver tests the ready flags (TDRE and RDRF) until a ready
condition appears (transmitter data register empty or receiver data register
full). If an error condition occurs on receive, the routine must clear the
error flags and take appropriate action, if any. If the /CTS line is used for
flow control, transmission of data is automatically stopped when /CTS
goes high because the TDRE flag is disabled. This prevents the driver from
transmitting more characters because it thinks the transmitter is not ready.
The transmitter will still function with /CTS high, but exercise care
because TDRE is not available to synchronize loading the data register
(TDR) properly.
An interrupt-driven port works as follows. The program enables the
receiver interrupt as long as it wants to receive characters. The transmitter
interrupt is enabled only while characters are waiting in the output buffer.
When an interrupt occurs, the interrupt routine must determine the cause:
receiver data register full, transmitter data register empty, receiver error, or
/DCD0
pin high (channel 0 only). None of these interrupts is edge-
triggered. Another interrupt will occur immediately if interrupts are re-
enabled without disabling the condition causing the interrupt. The signal
/DCD0
is grounded on the OP7100.
Table 3-3 lists the interrupt vectors.
Table 3-3. Serial Port Interrupt Vectors
Address
Name
Description
0E
SER0_VEC
Z180 Serial Port 0 (higher priority)
10
SER1_VEC
Z180 Serial Port 1
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