參數(shù)資料
型號: 20-101-0732
廠商: Rabbit Semiconductor
文件頁數(shù): 5/126頁
文件大小: 0K
描述: INTERFACE SMART SCREEN OP7100
標準包裝: 1
系列: SBC
模塊/板類型: 單板計算機模塊
適用于相關(guān)產(chǎn)品: OP7100
其它名稱: 20-101-732
20-101-732-ND
OP7100
102
Memory, I/O Map, and Interrupt Vectors
Table C-2. Z180 Internal I/O Registers Addresses 0x00–0x3F
Address
Name
Description
0x00
CNTLA0
Serial Channel 0, Control Register A
0x01
CNTLA1
Serial Channel 1, Control Register A
0x02
CNTLB0
Serial Channel 0, Control Register B
0x03
CNTLB1
Serial Channel 1, Control Register B
0x04
STAT0
Serial Channel 0, Status Register
0x05
STAT1
Serial Channel 1, Status Register
0x06
TDR0
Serial Channel 0, Transmit Data Register
0x07
TDR1
Serial Channel 1, Transmit Data Register
0x08
RDR0
Serial Channel 0, Receive Data Register
0x09
RDR1
Serial Channel 1, Receive Data Register
0x0A
CNTR
Clocked Serial Control Register
0x0B
TRDR
Clocked Serial Data Register
0x0C
TMDR0L
Timer Data Register Channel 0, least
0x0D
TMDR0H
Timer Data Register Channel 0, most
0x0E
RLDR0L
Timer Reload Register Channel 0, least
0x0F
RLDR0H
Timer Reload Register Channel 0, most
0x10
TCR
Timer Control Register
0x11–0x13
Reserved
0x14
TMDR1L
Timer Data Register Channel 1, least
0x15
TMDR1H
Timer Data Register Channel 1, most
0x16
RLDR1L
Timer Reload Register Channel 1, least
0x17
RLDR1H
Timer Reload Register Channel 1, most
continued…
Memory Map
Input/Output Select Map
The Dynamic C library functions IBIT, ISET, and IRES in the BIOS.LIB
library allow bits in the I/O registers to be tested, set, and cleared. Both
16-bit and 8-bit I/O addresses can be used.
Z180 Internal Input/Output Registers Addresses 00-3F
The internal registers for the I/O devices built into to the Z180 processor
occupy the first 40 (hex) addresses of the I/O space. These addresses are
listed in Table C-2.
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