參數(shù)資料
型號： 20-101-0732
廠商： Rabbit Semiconductor
文件頁數(shù)： 68/126頁
文件大?。?/td> 0K
描述： INTERFACE SMART SCREEN OP7100
標(biāo)準(zhǔn)包裝： 1
系列： SBC
模塊/板類型： 單板計算機模塊
適用于相關(guān)產(chǎn)品： OP7100
其它名稱： 20-101-732
20-101-732-ND
OP7100
46
Hardware
CTS1E (CTS Enable, Channel 1)
The signals RXS and CTS1 are multiplexed on the same pin. A 1 stored in
this bit makes the pin serve the CTS1 function. A 0 selects the RXS
function. (The pin RXS is the CSI/O data receive pin.) When RXS is
selected, the CTS line has no effect.
RIE (Receiver Interrupt Enable)
A 1 enables receiver interrupts and 0 disables them. A receiver interrupt is
requested under any of the following conditions: /DCD0 (Channel 0 only),
RDRF (read data register full), OVRN (overrun), PE (parity error), and FE
(framing error). The condition causing the interrupt must be removed be-
fore the interrupts are re-enabled, or another interrupt will occur. Reading
the receiver data register (RDR) clears the RDRF flag. The EFR bit in
CNTLA is used to clear the other error flags.
FE (Framing Error)
A stop bit was missing, indicating scrambled data. This bit is cleared by the
EFR bit in CNTLA.
PE (Parity Error)
Parity is tested only if MOD1 in CNTLA is set. This bit is cleared by the
EFR bit in CNTLA.
OVRN (Overrun Error)
Overrun occurs when bytes arrive faster than they can be read from the
receiver data register. The receiver shift register (RSR) and receiver data
register (RDR) are both full. This bit is cleared by the EFR bit in CNTLA.
RDRF (Receiver Data Register Full)
This bit is set when data is transferred from the receiver shift register to the
receiver data register. It is set even when one of the error flags is set, in
which case defective data is still loaded to RDR. The bit is cleared when
the receiver data register is read, when the /DCD0 input pin is high, and by
RESET and IOSTOP.
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