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| 型號： | 22505_1 |
| 英文描述： | AMD Test Interface Port Board Schematics? 149KB (PDF) |
| 中文描述： | AMD測試接口端口板原理圖？ 149KB（PDF格式） |
| 文件頁數(shù)： | 12/78頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | 22505_1 |
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Test Interface Port Board User’s Manual
xii
Eight discrete TTL/CMOS outputs (can connect directly to a logic analyzer).
Eight inputs connected to a DIP switch and header.
A reset button that resets the target.
An 8-bit DIP Flash memory, socketed to allow for upgrading.
A jumper block (JP1) for selecting between internal (TIP board) or external
(host board) Flash memory.
A flexible interface for simple and inexpensive connection to a target board.
An interrupt button.
Five interrupt sources on the board: two serial ports, the parallel port, the
Ethernet controller port, and the user-interrupt button. All these interrupts go to
the main interface connector separately. In addition, all these interrupts are logic
ORed into a single signal that also goes to the connector.
A macro array CMOS high-density/high-performance (MACH) device that
provides individual chip selects for each on-board peripheral device (except the
Ethernet controller port).
Support for 16-bit addressing or 8-bit addressing, selected with the SW3 switch.
Five programmable registers for controlling the TIP board’s operation.
Documentation
The
AMD Test Interface Port B
oard User’s Manual
, order #22505, provides
information on the system and board features, functionality, and interfaces.
Additional information can be found in the documentation listed on page xiii.
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