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| 型號(hào)： | 22505_1 |
| 英文描述： | AMD Test Interface Port Board Schematics? 149KB (PDF) |
| 中文描述： | AMD測(cè)試接口端口板原理圖？ 149KB（PDF格式） |
| 文件頁數(shù)： | 36/78頁 |
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Test Interface Port Board User’s Manual
2-12
Programming the Parallel Port
The TI TL16C552 parallel port interface is controlled primarily by software and
provides all the status inputs, control outputs, and the control signals necessary for
the external parallel port data buffers. Communication between the host and the
peripheral is asynchronous. The parallel port data path is external to the
microcontroller. The parallel port can be physically mapped to one of two different
I/O locations or can be completely disabled. Only edge-triggered interrupts are
supported.
The parallel port can connect to a Centronics-style printer interface. The parallel
port is selected when chip select 2 (CS2) is low. The state of the read (IOR) and
write (IOW) terminal controls the read or write function of the register. The Read
Data register controls when the microprocessor can read information on the parallel
bus.
The parallel port interface is mapped to 320h–322h (8-bit) or 340h–344h (16-bit).
The following direct-mapped registers are available.
Read Data Register:
This register enables the microprocessor to read the
information on the parallel bus.
Read Status Register:
This register enables the microprocessor to read the
status of the printer in the six most significant bits. The status bits are: printer
busy (BSY); acknowledge (ACK), a handshake function; paper empty (PE);
printer selected (SLCT); error (ERR); and printer interrupt (PRINT).
Read Control Register:
This register enables the state of the control lines to
be read.
Write Data Register:
This register enables the microprocessor to write a byte
to the parallel bus.
Write Control Register:
This register sets the state of the control lines. These
states are: direction (DIR); interrupt enable (IN2 EN); select in (SLIN); initialize
the printer (INIT); autofeed the paper (AFD); and strobe (STR), which informs
the printer of the presence of a valid byte on the parallel bus.
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