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| 型號(hào)： | 22505_1 |
| 英文描述： | AMD Test Interface Port Board Schematics? 149KB (PDF) |
| 中文描述： | AMD測試接口端口板原理圖？ 149KB（PDF格式） |
| 文件頁數(shù)： | 32/78頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | 22505_1 |
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Test Interface Port Board User’s Manual
2-8
Interrupts
The serial port supports the standard UART interrupts as follows:
Received Data Available
Transmit Holding Register Empty
Modem Status
Receiver Line Status
If two interrupt sources are pending simultaneously, only the highest priority
interrupt is indicated by the ID2–ID0 field of the Interrupt ID Register. When the
interrupt source is cleared, a subsequent read from this port will return the next
highest priority interrupt source.
Registers
The registers store three types of information: control, status, and data. The divisor
latch access bit (DLAB) in the Line Control register (bit 7) is used with the address,
read, and write inputs to select the register that is written to or read from. The
Transmit Holding register and Receive Buffer register are data registers that hold
from five to eight bits of data. If less than eight bits of data are transmitted, data is
right justified to the least significant bit. Bit 0 of a data word is always the first
serial data bit received and transmitted. The data registers are double-buffered so
that read and write operations can be performed when the serial port is performing
the parallel-to-serial or serial-to-parallel conversion.
The following registers are available on the serial port. The bits for these registers
are described in the TI TL16C552 Specification.
Line Control Register:
This register is used to configure the format of the
UART frame for data transfer, including character length, stop bits, and parity.
Divisor Latch LSB:
This register holds the least significant byte of a 16-bit
baud rate clock divisor that is used to generate the 16x baud clock (when DLAB
is 1).
Divisor Latch MSB:
This register holds the most significant byte of the clock
divisor (when DLAB is 0).
Transmitter Holding Register:
The byte to be transmitted is written to this
write-only register (when DLAB is 0).
Receive Buffer Register:
The received byte is read from this read-only register
(when DLAB is 0). This register shares an address with the Transmit Holding
Register.
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