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參數(shù)資料
| 型號(hào)： | 22505_1 |
| 英文描述： | AMD Test Interface Port Board Schematics? 149KB (PDF) |
| 中文描述： | AMD測(cè)試接口端口板原理圖？ 149KB（PDF格式） |
| 文件頁數(shù)： | 31/78頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | 22505_1 |
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Test Interface Port Board User’s Manual
2-7
Programming the Serial Ports
This section contains general information about the programming operations and
functions of the serial ports including operating mode, UART operation, interrupts,
and registers.
Operating Mode
The 16550-compatible UART mode (FIFO mode) contains two 16-byte FIFOs for
transmitting and receiving to off-load the CPU from repetitive service routines.
The CPU can write 16 bytes to the transmit FIFO and use the THRE interrupt or
poll the THRE bit to trigger another 16 bytes. The receive FIFO has a
programmable trigger level that can interrupt the CPU at 1, 4, 8, or 16 bytes present.
Writing a byte to a full transmit FIFO results in the last byte being lost. If the receive
FIFO is full, receiving one more character generates an overrun error. The last
character received is lost. The remaining 16 bytes in the FIFO are unchanged.
UART Operation
The UART converts serial data received on the serial input line (SIN) into parallel
data that can be processed by the microcontroller. The UART also converts parallel
data into serial data for transmission off the chip on the serial output line (SOUT).
Data can be transmitted and received at the same time.
To generate the baud rate of the transfer, the UART clock is divided by a divisor
value chosen by the programmer. The UART baud-rate generator automatically
calculates the baud rate from the divisor value that is programmed into the two
baud rate divisor registers (divisor latch LSB and divisor latch MSB). These
registers are read at initialization to set the baud rate for the transfer.
Each byte of data is transferred using a format called a frame. The transmitter and
receiver must agree on the frame format, in addition to the baud rate, or the
transmission is not successful. The frame format is determined by the value written
into the Line Control register. A frame consists of a start bit, five to eight data bits,
an optional parity bit, and either 1, 1.5, or 2 stop bits. Transmission of a frame is
initiated when software writes a byte to the Transmit Holding register. Reception
of a frame is initiated when a start bit is received (the SIN input is driven Low for
one baud-rate clock period). This start bit allows the receiver to synchronize its
clock with the sender’s clock. Errors are reported in the Line Status register.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 225-052-4.000M | 制造商:PCSI 功能描述:HC49-4.0000M |
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