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| 型號： | 22505_1 |
| 英文描述： | AMD Test Interface Port Board Schematics? 149KB (PDF) |
| 中文描述： | AMD測試接口端口板原理圖？ 149KB（PDF格式） |
| 文件頁數(shù)： | 54/78頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | 22505_1 |
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Test Interface Port Board User’s Manual
2-30
Interrupts
WARNING: The peripheral interrupt signals on the TIP board are not
terminated. As a result, the software must ensure that each peripheral
interrupt is enabled so the interrupt input to the OR gate that is driving
the MAIN_IRQ signal is not floating. Refer to the peripheral data sheets
for information about how this is done. Alternately, the target board
may use pull-down resistors on the peripheral interrupt signals.
The TIP board supports interrupts with the following features:
An interrupt push button (SW2)
Five interrupt sources on the board: two serial ports, the parallel port, the
Ethernet controller port, and the user-interrupt button
For designs that can accommodate all the individual signals and want to have
dedicated interrupts, the serial ports, parallel port, and Ethernet controller port have
individual interrupt signals going to the main interface connector (P1). For designs
that have limited connector space, these same signals are also logically ORed
together on the MAIN_IRQ signal, which is also routed to the main connector.
The interrupt generated by the interrupt push button is routed to the main connector
only through the MAIN_IRQ signal.
When the interrupt button is pressed, the
SW_IRQ signal (generated from the MACH), goes high causing the MAIN_IRQ
signal to also go high. The SW_IRQ signal will remain high until the Interrupt
Reset register (address 34Ah) in the MACH is written to. For the address of this
register, refer to “I/O Maps” on page 2-32.
MACH Device
The peripherals on the TIP board are interfaced to the host system through a macro
array CMOS high-density/high-performance (MACH) device that provides
individual chip selects for each on-board peripheral device (except the Ethernet
controller port). This interface gives the TIP board a degree of independence from
the host system. For a complete listing of the current MACH device code, see
Appendix A, “MACH Device Equations”.
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