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參數(shù)資料
| 型號： | 28F001BX-T |
| 廠商： | Intel Corp. |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 1兆位（128K的× 8）引導(dǎo)塊閃存 |
| 文件頁數(shù)： | 10/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | 28F001BX-T |
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28F001BX-T/28F001BX-B
Table 4. 28F001BX Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
SR.7
e
WRITE STATE MACHINE STATUS
1
e
Ready
0
e
Busy
SR.6
e
ERASE SUSPEND STATUS
1
e
Erase Suspended
0
e
Erase In Progress/Completed
SR.5
e
ERASE STATUS
1
e
Error in Block Erasure
0
e
Successful Block Erase
SR.4
e
PROGRAM STATUS
1
e
Error in Byte Program
0
e
Successful Byte Program
SR.3
e
V
PP
STATUS
1
e
V
PP
Low Detect; Operation Abort
0
e
V
PP
OK
SR.2–SR.0
e
RESERVED FOR FUTURE ENHANCE-
MENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
NOTES:
The Write State Machine Status Bit must first be checked
to determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to ‘‘1s’’ dur-
ing an erase attempt, an improper command sequence
was entered. Attempt the operation again.
If V
PP
low status is detected, the Status Register must be
cleared before another program or erase operation is at-
tempted.
The V
PP
Status bit, unlike an A/D converter, does not
provide continuous indication of V
PP
level. The WSM in-
terrogates the V
PP
level only after the program or erase
command sequences have been entered and informs the
system if V
PP
has not been switched on. The V
PP
Status
bit is not guaranteed to report accurate feedback be-
tween V
PPL
and V
PPH
.
Erase Setup/Erase Confirm
Commands
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command
Register, followed by the Erase Confirm command
(D0H). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State Machine,
invisible to the system. After receiving the two-com-
mand erase sequence, the 28F001BX automatically
outputs Status Register data when read (see Figure
10; Block Erase Flowchart). The CPU can detect the
completion of the erase event by checking the WSM
Status bit of the Status Register (SR.7).
When the Status Register indicates that erase is
complete, the Erase Status bit should be checked. If
erase error is detected, the Status Register should
be cleared. The Command Register remains in Read
Status Register Mode until further commands are is-
sued to it.
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased. Also, block erasure can only occur
when V
PP
e
V
PPH
. In the absence of this high volt-
age, memory contents are protected against era-
sure. If block erase is attempted while V
PP
e
V
PPL
,
the V
PP
Status bit will be set to ‘‘1’’. Erase attempts
while V
PPL
k
V
PP
k
V
PPH
produce spurious results
and should not be attempted.
Erase Suspend/Erase Resume
Commands
The Erase Suspend Command allows erase se-
quence interruption in order to read data from anoth-
er block of memory. Once the erase sequence is
started, writing the Erase Suspend command (B0H)
to the Command Register requests that the WSM
suspend the erase sequence at a predetermined
point in the erase algorithm. The 28F001BX contin-
ues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling
the WSM Status and Erase Suspend Status bits will
determine when the erase operation has been sus-
pended (both will be set to ‘‘1s’’).
At this point, a Read Array command can be written
to the Command Register to read data from blocks
other than that which is suspended
. The only oth-
er valid commands at this time are Read Status Reg-
ister (70H) and Erase Resume (D0H), at which time
the WSM will continue with the erase sequence. The
Erase Suspend Status and WSM Status bits of the
Status Register will be cleared. After the Erase Re-
sume command is written to it, the 28F001BX auto-
matically outputs Status Register data when read
(see Figure 11; Erase Suspend/Resume Flowchart).
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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